JAJSQ25
march 2023
DAC53004W
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics: Voltage Output
6.6
Electrical Characteristics: Current Output
6.7
Electrical Characteristics: Comparator Mode
6.8
Electrical Characteristics: General
6.9
Timing Requirements: I2C Standard Mode
6.10
Timing Requirements: I2C Fast Mode
6.11
Timing Requirements: I2C Fast Mode Plus
6.12
Timing Requirements: SPI Write Operation
6.13
Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
6.14
Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
6.15
Timing Requirements: GPIO
6.16
Timing Diagrams
6.17
Typical Characteristics: Voltage Output
6.18
Typical Characteristics: Current Output
6.19
Typical Characteristics: Comparator
6.20
Typical Characteristics: General
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Smart Digital-to-Analog Converter (DAC) Architecture
7.3.2
Digital Input/Output
7.3.3
Nonvolatile Memory (NVM)
7.3.4
Power Consumption
7.4
Device Functional Modes
7.4.1
Voltage-Output Mode
7.4.1.1
Voltage Reference and DAC Transfer Function
7.4.1.1.1
Internal Reference
7.4.1.1.2
External Reference
7.4.1.1.3
Power-Supply as Reference
7.4.2
Current-Output Mode
7.4.3
Comparator Mode
7.4.3.1
Programmable Hysteresis Comparator
7.4.3.2
Programmable Window Comparator
7.4.4
Fault-Dump Mode
7.4.5
Application-Specific Modes
7.4.5.1
Voltage Margining and Scaling
7.4.5.1.1
High-Impedance Output and PROTECT Input
7.4.5.1.2
Programmable Slew-Rate Control
7.4.5.1.3
PMBus Compatibility Mode
7.4.5.2
Function Generation
7.4.5.2.1
Triangular Waveform Generation
7.4.5.2.2
Sawtooth Waveform Generation
7.4.5.2.3
Sine Waveform Generation
7.4.6
Device Reset and Fault Management
7.4.6.1
Power-On Reset (POR)
7.4.6.2
External Reset
7.4.6.3
Register-Map Lock
7.4.6.4
NVM Cyclic Redundancy Check (CRC)
7.4.6.4.1
NVM-CRC-FAIL-USER Bit
7.4.6.4.2
NVM-CRC-FAIL-INT Bit
7.4.7
Power-Down Mode
7.5
Programming
7.5.1
SPI Programming Mode
7.5.2
I2C Programming Mode
7.5.2.1
F/S Mode Protocol
7.5.2.2
I2C Update Sequence
7.5.2.2.1
Address Byte
7.5.2.2.2
Command Byte
7.5.2.3
I2C Read Sequence
7.5.3
General-Purpose Input/Output (GPIO) Modes
7.6
Register Map
7.6.1
NOP Register (address = 00h) [reset = 0000h]
7.6.2
DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
7.6.3
DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
7.6.4
DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
7.6.5
DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
7.6.6
DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
7.6.7
DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
7.6.8
DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
7.6.9
COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
7.6.10
COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
7.6.11
COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
7.6.12
GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
7.6.13
CMP-STATUS Register (address = 23h) [reset = 0000h]
7.6.14
GPIO-CONFIG Register (address = 24h) [reset = 0000h]
7.6.15
DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
7.6.16
INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
7.6.17
SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
7.6.18
SRAM-DATA Register (address = 2Ch) [reset = 0000h]
7.6.19
DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
7.6.20
BRDCAST-DATA Register (address = 50h) [reset = 0000h]
7.6.21
PMBUS-PAGE Register [reset = 0300h]
7.6.22
PMBUS-OP-CMD-X Register [reset = 0000h]
7.6.23
PMBUS-CML Register [reset = 0000h]
7.6.24
PMBUS-VERSION Register [reset = 2200h]
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
ドキュメントの更新通知を受け取る方法
9.2
サポート・リソース
9.3
Trademarks
9.4
静電気放電に関する注意事項
9.5
用語集
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
YBH|16
MPBGAQ3
サーマルパッド・メカニカル・データ
発注情報
jajsq25_oa
8.4.2
Layout Example
Figure 8-3
Layout Example
Note: The ground and power planes have been omitted for clarity.