JAJSRM3 November   2023 DAC530A2W , DAC532A3W

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Voltage Output
    6. 5.6  Electrical Characteristics: Current Output
    7. 5.7  Electrical Characteristics: Comparator Mode
    8. 5.8  Electrical Characteristics: General
    9. 5.9  Timing Requirements: I2C Standard Mode
    10. 5.10 Timing Requirements: I2C Fast Mode
    11. 5.11 Timing Requirements: I2C Fast-Mode Plus
    12. 5.12 Timing Requirements: SPI Write Operation
    13. 5.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 5.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 5.15 Timing Requirements: GPIO
    16. 5.16 Timing Diagrams
    17. 5.17 Typical Characteristics: Voltage Output
    18. 5.18 Typical Characteristics: Current Output
    19. 5.19 Typical Characteristics: Comparator
    20. 5.20 Typical Characteristics: General
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 Digital Input/Output
      3. 6.3.3 Nonvolatile Memory (NVM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Voltage-Output Mode
        1. 6.4.1.1 Voltage Reference and DAC Transfer Function
          1. 6.4.1.1.1 Internal Reference
          2. 6.4.1.1.2 Power-Supply as Reference
      2. 6.4.2 Current-Output Mode
      3. 6.4.3 Comparator Mode
        1. 6.4.3.1 Programmable Hysteresis Comparator
        2. 6.4.3.2 Programmable Window Comparator
      4. 6.4.4 Fault-Dump Mode
      5. 6.4.5 Application-Specific Modes
        1. 6.4.5.1 Voltage Margining and Scaling
          1. 6.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 6.4.5.1.2 Programmable Slew-Rate Control
        2. 6.4.5.2 Function Generation
          1. 6.4.5.2.1 Triangular Waveform Generation
          2. 6.4.5.2.2 Sawtooth Waveform Generation
          3. 6.4.5.2.3 Sine Waveform Generation
      6. 6.4.6 Device Reset and Fault Management
        1. 6.4.6.1 Power-On Reset (POR)
        2. 6.4.6.2 External Reset
        3. 6.4.6.3 Register-Map Lock
        4. 6.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 6.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 6.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 6.4.7 General-Purpose Input/Output (GPIO) Modes
    5. 6.5 Programming
      1. 6.5.1 SPI Programming Mode
      2. 6.5.2 I2C Programming Mode
        1. 6.5.2.1 F/S Mode Protocol
        2. 6.5.2.2 I2C Update Sequence
          1. 6.5.2.2.1 Address Byte
          2. 6.5.2.2.2 Command Byte
        3. 6.5.2.3 I2C Read Sequence
  8. 7 Register Map
    1. 7.1  NOP Register (address = 00h) [reset = 0000h]
    2. 7.2  DAC-0-MARGIN-HIGH Register (address = 0Dh) [reset = 0000h]
    3. 7.3  DAC-1-MARGIN-HIGH Register (address = 13h) [reset = 0000h]
    4. 7.4  DAC-2-MARGIN-HIGH Register (address = 01h) [reset = 0000h]
    5. 7.5  DAC-0-MARGIN-LOW Register (address = 0Eh) [reset = 0000h]
    6. 7.6  DAC-1-MARGIN-LOW Register (address = 14h) [reset = 0000h]
    7. 7.7  DAC-2-MARGIN-LOW Register (address = 02h) [reset = 0000h]
    8. 7.8  DAC-0-GAIN-CONFIG Register (address = 0Fh) [reset = 0000h]
    9. 7.9  DAC-1-GAIN-CMP-CONFIG Register (address = 15h) [reset = 0000h]
    10. 7.10 DAC-2-GAIN-CONFIG Register (address = 03h) [reset = 0000h]
    11. 7.11 DAC-1-CMP-MODE-CONFIG Register (address = 17h) [reset = 0000h]
    12. 7.12 DAC-0-FUNC-CONFIG Register (address = 12h) [reset = 0000h]
    13. 7.13 DAC-1-FUNC-CONFIG Register (address = 18h) [reset = 0000h]
    14. 7.14 DAC-2-FUNC-CONFIG Register (address = 06h) [reset = 0000h]
    15. 7.15 DAC-0-DATA Register (address = 1Bh) [reset = 0000h]
    16. 7.16 DAC-1-DATA Register (address = 1Ch) [reset = 0000h]
    17. 7.17 DAC-2-DATA Register (address = 19h) [reset = 0000h]
    18. 7.18 COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
    19. 7.19 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
    20. 7.20 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
    21. 7.21 GENERAL-STATUS Register (address = 22h) [reset = 20h, DEVICE-ID, VERSION-ID]
    22. 7.22 CMP-STATUS Register (address = 23h) [reset = 000Ch]
    23. 7.23 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
    24. 7.24 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
    25. 7.25 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
    26. 7.26 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
    27. 7.27 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
    28. 7.28 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics: Voltage Output

all minimum and maximum specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C,
3 V ≤ VDD ≤ 5.5 V, VDD as reference, gain = 1 ×, voltage-output DAC pin (VOUTx) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution 10 Bits
INL Integral nonlinearity(1) –1.25 1.25 LSB
DNL Differential nonlinearity(1) –1 1 LSB
Zero-code error(2) Code 0d into DAC, VDD = 5.5 V 6 12 mV
Code 0d into DAC, internal VREF, gain = 4 ×,
VDD = 5.5 V		 6 15
Zero-code-error temperature coefficient(2) ±10 µV/°C
Offset error(2) 3 V ≤ VDD ≤ 5.5 V, VFB pin shorted to VOUT, DAC code: 8d for 10-bit resolution –0.5 0.25 0.5 %FSR
Offset-error temperature coefficient(2) VFB pin shorted to VOUT, DAC code: 8d for 10-bit resolution ±0.0003 %FSR/°C
Gain error(2) Between end-point codes: 8d to 1016d for 10-bit resolution –0.5 0.25 0.5 %FSR
Gain-error temperature coefficient(2) Between end-point codes: 8d to 1016d for 10-bit resolution ±0.0008 %FSR/°C
Full-scale error(2) 3 V ≤ VDD ≤ 5.5 V, DAC at full scale –0.5 0.5 %FSR
Full-scale-error temperature coefficient(2) DAC at full scale ±0.0008 %FSR/°C
OUTPUT
Output voltage 0 VDD V
CL Capacitive load(3) RL = infinite, phase margin = 30° 200 pF
Phase margin = 30° 1000
Short-circuit current VDD = 3 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 50 mA
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 60
Output-voltage headroom(3) To VDD, DAC output unloaded, internal reference = 1.21 V), VDD ≥ 1.21 V × gain + 0.2 V 0.2 V
To VDD and to AGND, DAC output unloaded 0.8 %FSR
To VDD and to AGND, ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 3 V 10
ZO VFB dc output impedance(4) DAC output enabled, internal reference (gain = 1.5 × or 2 ×) or VDD as reference (gain = 1 ×) 400 500 600 kΩ
DAC output enabled, internal VREF, gain = 3 × or 4 × 325 400 485
Power-supply rejection ratio (dc) Internal VREF, gain = 2 ×, DAC at midscale,
VDD = 5 V ±10%		 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V 20 µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4 × 25
Slew rate VDD = 5.5 V 0.3 V/µs
Power-on glitch magnitude At start-up, DAC output disabled 75 mV
At start-up, DAC output disabled, RL = 100 kΩ 200
Output-enable glitch magnitude DAC output disabled to enabled, DAC registers at zero scale, RL = 100 kΩ 250 mV
Vn Output noise voltage
(peak-to-peak)		 f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 50 µVPP
Internal VREF, gain = 4 ×, f = 0.1 Hz to 10 Hz,
DAC at midscale, VDD = 5.5 V		 90
Output noise density f = 1 kHz, DAC at midscale, VDD = 5.5 V 0.35 µV/√Hz
Internal VREF, gain = 4 ×, f = 1 kHz, DAC at midscale, VDD = 5.5 V 0.9
Power-supply rejection ratio (ac)(4) Internal VREF, gain = 4 ×, 200-mV 50-Hz or 60-Hz sine wave superimposed on power supply voltage, DAC at midscale -68 dB
Code-change glitch impulse ±1-LSB change around midscale, including feedthrough 10 nV-s
Code-change glitch impulse magnitude ±1-LSB change around midscale, including feedthrough 15 mV
POWER
IDD Current flowing into VDD(2) (5) DAC532A3W: Normal operation, DACs at full scale, digital pins static 150 µA/ch
DAC530A2W: Normal operation, DACs at full scale, digital pins static 65 85
(1) Measured with DAC output unloaded. For internal reference VDD ≥ 1.21 × gain + 0.2 V, between end-point codes: 8d to 1016d for 10-bit resolution.
(2) Measured with DAC output unloaded.
(3) Specified by design and characterization, not production tested.
(4) Specified with 200-mV headroom with respect to reference value when internal reference is used.
(5) The total power consumption is calculated by IDD × (total number of channels powered on) + (sleep-mode current).