JAJSK36A October 2020 – September 2023 DAC43701-Q1 , DAC53701-Q1
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FUNC_ CONFIG |
DEVICE_ LOCK |
EN_ PMBUS |
CODE_STEP | SLEW_RATE | DAC_PDN | REF_EN | DAC_SPAN | ||||||||
R/ W-00 | R/W-0 | R/W-0 | R/W-000 | R/W-Fh | R/W-10h | R/W-0 | R/W-00 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | FUNC_CONFIG | R/W | 00 | 00: Generates a triangle wave
between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h)
code with slope defined by SLEW_RATE and CODE_STEP bits. 01: Generates Saw-Tooth wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code, with rising slope defined by SLEW_RATE and CODE_STEP bits and immediate falling edge. 10: Generates Saw-Tooth wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code, with falling slope defined by SLEW_RATE and CODE_STEP bits and immediate rising edge. 11: Generates a square wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code with pulse high and low period defined by SLEW_RATE bits. |
13 | DEVICE_LOCK | R/W | 0 | 0: Device not locked 1: Device locked, the device locks all the registers. This bit can be overwritten (unlock device) by writing 0101 to the DEVICE_UNLOCK_CODE bits (address D3h) |
12 | EN_PMBUS | R/W | 0 | 0: PMBus mode disabled 1: PMBus mode enabled |
11:9 | CODE_STEP | R/W | 000 | Code step for programmable
slew rate control. 000: Code step size = 1 LSB (default) 001: Code step size = 2 LSB 010: Code step size = 3 LSB 011: Code step size = 4 LSB 100: Code step size = 6 LSB 101: Code step size = 8 LSB 110: Code step size = 16 LSB 111: Code step size = 32 LSB |
8:5 | SLEW_RATE | R/W | Fh | Slew rate for programmable
slew rate control. 0000: 25.6 µs (per step) 0001: 32 µs (per step) 0010: 38.4 µs (per step) 0011: 44.8 µs (per step) 0100: 204.8 µs (per step) 0101:256 µs (per step) 0110: 307.2 µs (per step) 0111: 819.2 µs (per step) 1000: 1.6384 ms (per step) 1001: 2.4576 ms (per step) 1010: 3.2768 ms (per step) 1011: 4.9152 ms (per step) 1100: 12 µs (per step) 1101: 8 µs (per step) 1110: 4 µs (per step) 1111: No slew (default) |
4:3 | DAC_PDN | R/W | 10 | 00: Power up 01: Power down to 10 kΩ 10: Power down to high impedance (default) 11: Power down to 10 kΩ |
2 | REF_EN | R/W | 0 | 0: Internal reference
disabled, VDD is DAC reference voltage, DAC output range
from 0 V to VDD. 1: Internal reference enabled, DAC reference = 1.21 V, DAC output range is a function of DAC_SPAN. |
1:0 | DAC_SPAN | R/W | 00 | Only applicable when internal
reference is enabled. 00: Reference to VOUT gain = 1.5 × 01: Reference to VOUT gain = 2 × 10: Reference to VOUT gain = 3 × 11: Reference to VOUT gain = 4 × |