JAJSJI1E October   2020  – January 2021 DAC5652

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Rationgs
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Resistance Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics, AC
    8. 6.8  Electrical Characteristics, DC
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Inputs and Timing
      1. 7.1.1 Digital Inputs
      2. 7.1.2 Input Interfaces
      3. 7.1.3 Dual-Bus Data Interface and Timing
      4. 7.1.4 Single-Bus Interleaved Data Interface and Timing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Transfer Function
      2. 8.3.2 Analog Outputs
      3. 8.3.3 Output Configurations
      4. 8.3.4 Differential With Transformer
      5. 8.3.5 Single-Ended Configuration
      6. 8.3.6 Reference Operation
        1. 8.3.6.1 Internal Reference
        2. 8.3.6.2 External Reference
      7. 8.3.7 Gain Setting Option
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. 9 Application Information Disclaimer
    1. 9.1 Application Informmation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.1 DAC Transfer Function

Each of the DACs in the DAC5652 has a set of complementary current outputs, IOUT1 and IOUT2. The full-scale output current, IOUTFS, is the summation of the two complementary output currents:

Equation 1. GUID-F6742B5A-FA0A-417A-AA14-89E40192BE15-low.gif

The individual output currents depend on the DAC code and can be expressed as:

Equation 2. GUID-D8AB2FE2-6ACD-4311-B4B0-4DD080DF89C5-low.gif
Equation 3. GUID-DC053107-0352-48AD-AE72-A1DC8ACFDAEE-low.gif

where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the reference current IREF, which is determined by the reference voltage and the external setting resistor (RSET).

Equation 4. GUID-B73315FF-0D90-45E6-9223-BC5BF86EE65E-low.gif

In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltage develops at each output according to:

Equation 5. GUID-1C5307CF-B91C-4BF0-AF00-47A233E68555-low.gif
Equation 6. GUID-D25C2EB2-A7C3-4E45-A6F8-014A16153112-low.gif

The value of the load resistance is limited by the output compliance specification of the DAC5652. To maintain specified linearity performance, the voltage for IOUT1 and IOUT2 must not exceed the maximum allowable compliance range.

The total differential output voltage is:

Equation 7. GUID-44E6BFFE-7A9C-4B8C-8727-D3E92B6CCD47-low.gif
Equation 8. GUID-5CB53CF7-9116-412E-974E-73C88F24B658-low.gif