SGLS386F January   2009  – October 2014 DAC5670-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Digital Electrical Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs
      2. 8.3.2 DLL Usage
      3. 8.3.3 Clock Input
      4. 8.3.4 DAC Transfer Function
      5. 8.3.5 Reference Operation
      6. 8.3.6 Analog Current Outputs
      7. 8.3.7 Sleep Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Format
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Definitions of Specifications and Terminology
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DAC5670 is a 14-bit DAC with max input rate of 2.4 GSPS. The DAC5670 is also suitable to operate at lower sample rates without the use of the DLL for input interface timing.

9.2 Typical Application

appinfocircuit_gls386.gifFigure 26. Current Steering DAC5670

9.2.1 Design Requirements

This example uses DACCLK rate of 2 GHz with signal output at 300 MHz.

9.2.2 Detailed Design Procedure

This example is outputting a 300-MHz tone with 2-GHz sample rate. Data is applied to both A and B ports at 1-GHz dual data rate. Full scale IOUT current set to 19.2 mA.

Equation 10. IOUTFS= 19.2 mA = 32 × IBIAS32 × VREFIO / RBIAS= 32 × 1.2 V / 2 kΩ

Device settings:

  • RESTART low
  • LVDS_HTB (pattern generator source dependent)
  • INV_CLK as necessary for DLL lock
  • SLEEP low
  • NORMAL high
  • A_ONLY low
  • A_ONLY_INV low
  • A_ONLY_ZS low
  • DA_P[0:13], DA_N[0:13], DB_P[0:13],DB_N[0:13] sourced from pattern generator generating 300-MHz tone with 65536 sample depth
  • RBIAS 2 kΩ to GND

9.2.3 Application Curves

2GHz_300MHz_tone_gls386.gif
Figure 27. 2-GHz 300-MHz Tone
D002_SGLS386.gif
Figure 28. DAC5670 Bandwidth 2 GSPS