SBAS334D November   2004  – July 2016 DAC5675A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description Continued
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Digital Specifications
    8. 7.8 Operational Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs
      2. 8.3.2 Clock Input
      3. 8.3.3 Supply Inputs
      4. 8.3.4 DAC Transfer Function
      5. 8.3.5 Reference Operation
      6. 8.3.6 Analog Current Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
    6. 12.6 Device Nomenclature
      1. 12.6.1 Definitions of Specifications and Terminology
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range AVDD (2) –0.3 +3.6 V
DVDD (3) –0.3 +3.6 V
AVDD to DVDD –0.7 +0.7 V
Voltage between AGND and DGND –0.3 +0.5 V
CLK, CLKC(2) –0.3 AVDD + 0.3 V
Digital input D[13:0]A, D[13:0]B(3), SLEEP –0.3 DVDD + 0.3 V
IOUT1, IOUT2(2) –1.0 AVDD + 0.3 V
EXTIO, BIAS(2) –1.0 AVDD + 0.3 V
Peak input current (any input) 20 mA
Peak total input current (all inputs) -30 mA
Operating free-air temperature range, TA –40 +85 °C
Storage temperature range –65 +150 °C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure outside of absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to AGND.
(3) Measured with respect to DGND.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supplies
AVDD 3.15 3.3 3.6 V
DVDD 3.15 3.3 3.6 V
I(AVDD) Analog supply current 115 mA
I(DVDD) Digital supply current 85 mA
Analog Output
IO(FS) Full-scale output current 2 20 mA
Output compliance range AVDD -1 AVDD + 0.3 V
Clock Interface (CLK, CLKC)
CLKINPUT Frequency 400 MHz
|CLK – CLKC| 0.4 0.8 VPP
Clock duty cycle 40% 60%
VCM Common-mode voltage range 1.6 2 2.4 V

7.4 Thermal Information

THERMAL METRIC(1) DAC5675A UNIT
PHP (HTQFP)
48 PINS
RθJA Junction-to-ambient thermal resistance 31.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 13.0 °C/W
RθJB Junction-to-board thermal resistance 10.9 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 10.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the SPRA953Semiconductor and IC Package Thermal Metrics application report.

7.5 DC Electrical Characteristics

Over operating free-air temperature range. Typical values at +25°C, AVDD = 3.3V, DVDD = 3.3V, IO(FS) = 20mA, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 14 Bit
DC Accuracy(1)
INL Integral nonlinearity TMIN to TMAX –4 ±1.5 4 LSB
DNL Differential nonlinearity –2 ±0.6 2 LSB
Monotonicity Monotonic 12b Level
Analog Output
IO(FS) Full-scale output current 2 20 mA
Output compliance range AVDD = 3.15V to 3.45V, IO(FS) = 20mA AVDD – 1 AVDD +0.3 V
Offset error 0.01 %FSR
Gain error Without internal reference –10 5 10 %FSR
With internal reference –10 2.5 10 %FSR
Output resistance 300 kΩ
Output capacitance 5 pF
Reference Output
V(EXTIO) Reference voltage 1.17 1.23 1.29 V
Reference output current(2) 100 nA
Reference Input
V(EXTIO) Input reference voltage 0.6 1.2 1.25 V
Input resistance 1 MΩ
Small-signal bandwidth 1.4 MHz
Input capacitance 100 pF
Temperature Coefficients
Offset drift 12 ppm of FSR/°C
Δ V(EXTIO) Reference voltage drift ±50 ppm/°C
Power Supply
AVDD Analog supply voltage 3.15 3.3 3.6 V
DVDD Digital supply voltage 3.15 3.3 3.6 V
I(AVDD) Analog supply current(3) 115 mA
I(DVDD) Digital supply current(3) 85 mA
PD Power dissipation Sleep mode 18 mW
PD Power dissipation AVDD = 3.3V, DVDD = 3.3V 660 900 mW
APSRR Analog and digital power- supply rejection ratio AVDD = 3.15V to 3.45V –0.5 ±0.1 0.5 %FSR/V
DPSRR –0.5 ±0.1 0.5 %FSR/V
(1) Measured differential at IOUT1 and IOUT2; 25Ω to AVDD.
(2) Use an external buffer amplifier with high impedance input to drive any external load.
(3) Measured at fCLK = 400MSPS and fOUT = 70MHz.

7.6 AC Electrical Characteristics

Over operating free-air temperature range. Typical values at +25°C, AVDD = 3.3V, DVDD = 3.3V, IO(FS) = 20mA, differential transformer-coupled output, 50Ω doubly-terminated load, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Output
fCLK Output update rate 400 MSPS
ts(DAC) Output setting time to 0.1% Transition: code x2000 to x23FF 12 ns
tPD Output propagation delay 1 ns
tr(IOUT) Output rise time, 10% to 90% 300 ps
tf(IOUT) Output fall time, 90% to 10% 300 ps
Output noise(1) IOUTFS = 20mA 55 pA/√Hz
IOUTFS = 2mA 30 pA/√Hz
AC Linearity
THD Total harmonic distortion fCLK = 100MSPS, fOUT = 19.9MHz 73 dBc
fCLK = 160MSPS, fOUT = 41MHz 72 dBc
fCLK = 200MSPS, fOUT = 70MHz 68 dBc
fCLK = 400MSPS, fOUT = 20.1MHz 72 dBc
fCLK = 400MSPS, fOUT = 70MHz 71 dBc
fCLK = 400MSPS, fOUT = 140MHz 58 dBc
SFDR Spurious-free dynamic range to Nyquist fCLK = 100MSPS, fOUT = 19.9MHz 73 dBc
fCLK = 160MSPS, fOUT = 41MHz 73 dBc
fCLK = 200MSPS, fOUT = 70MHz 70 dBc
fCLK = 400MSPS, fOUT = 20.1MHz 73 dBc
fCLK = 400MSPS, fOUT = 70MHz 74 dBc
fCLK = 400MSPS, fOUT = 140MHz 60 dBc
SFDR Spurious-free dynamic range within a window, 5MHz span fCLK = 100MSPS, fOUT = 19.9MHz 88 dBc
fCLK = 160MSPS, fOUT = 41MHz 87 dBc
fCLK = 200MSPS, fOUT = 70MHz 82 dBc
fCLK = 400MSPS, fOUT = 20.1MHz 87 dBc
fCLK = 400MSPS, fOUT = 70MHz 82 dBc
fCLK = 400MSPS, fOUT = 140MHz 75 dBc
ACPR Adjacent channel power ratio WCDMA with 3.84MHz BW, 5MHz channel spacing fCLK = 122.88MSPS, IF = 30.72MHz(2) 73 dB
fCLK = 245.76MSPS, IF = 61.44MHz(3) 71 dB
fCLK = 399.32MSPS, IF = 153.36MHz(4) 65 dB
IMD Two-tone intermodulation to Nyquist (each tone at -6dBfs) fCLK = 400MSPS, fOUT1 = 70MHz,
fOUT2 = 71MHz		 73 dBc
fCLK = 400MSPS, fOUT1 = 140MHz,
fOUT2 = 141MHz		 62 dBc
Four-tone intermodulation, 15MHz span, missing center tone (each tone at -16dBfs) fCLK = 156MSPS, fOUT = 15.6, 15.8, 16.2, 16.4MHz 82 dBc
fCLK = 400MSPS, fOUT = 68.1, 69.3, 71.2, 72MHz 74 dBc
(1) Noise averaged up to 400MHz when operating at 400MSPS.
(2) See Figure 9.
(3) See Figure 10.
(4) See Figure 12

7.7 Digital Specifications

Over operating free-air temperature range. Typical values at +25°C, AVDD = 3.3V, DVDD = 3.3V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS Interface: nodes D[13:0]A, D[13:0]B
VITH+ Positive-going differential input voltage threshold See LVDS min/max threshold voltages table 100 mV
VITH- Negative-going differential input voltage threshold -100 mV
ZT Internal termination impedance 90 110 132 Ω
CI Input capacitance 2 pF
CMOS Interface (SLEEP):
VIH High-level input voltage 2 3.3 V
VIL Low-level input voltage 0 0.8 V
IIH High-level input current –100 100 µA
IIL Low-level input current –10 10 µA
Input capacitance 2 pF
Clock Interface (CLK, CLKC):
|CLK-CLKC| Clock differential input voltage 0.4 0.8 VPP
Clock duty cycle 40% 60%
VCM Common-mode voltage range 2 ±20% V
Input resistance Node CLK, CLKC 670 Ω
Input capacitance Node CLK, CLKC 2 pF
Input resistance Differential 1.3 kΩ
Input capacitance Differential 1 pF
Timing
tSU Input setup time 1.5 ns
tH Input hold time 0 ns
tDD Digital delay time (DAC latency) 3 clk

7.8 Operational Characteristics(1)

Over operating free-air temperature range, AVDD = 3.3V, DVDD = 3.3V, IO(FS) = 20mA, unless otherwise noted.
APPLIED
VOLTAGES		 RESULTING
DIFFERENTIAL
INPUT VOLTAGE		 RESULTING
COMMON-MODE
INPUT VOLTAGE		 LOGICAL BIT
BINARY
EQUIVALENT		 COMMENT
VA [V] VB [V] VA,B [mV] VCOM [V]
1.25 1.15 100 1.2 1 Operation with minimum differential voltage (±100mV) applied to the complementary inputs versus common-mode range
1.15 1.25 –100 1.2 0
2.4 2.3 100 2.35 1
2.3 2.4 –100 2.35 0
0.1 0 100 0.05 1
0 0.1 –100 0.05 0
1.5 0.9 600 1.2 1 Operation with maximum differential voltage (±600mV) applied to the complementary inputs versus common-mode range
0.9 1.5 –600 1.2 0
2.4 1.8 600 2.1 1
1.8 2.4 –600 2.1 0
0.6 0 600 0.3 1
0 0.6 –600 0.3 0
(1) Specifications subject to change.
DAC5675A td01_bas334.gif Figure 1. Timing Diagram
DAC5675A td02_lvds_bas334.gif Figure 2. LVDS Timing Test Circuit and Input Test Levels

7.9 Typical Characteristics

DAC5675A tc_dnl-inpt_bas334.gif Figure 3. Differential Non-Linearity (DNL) vs Input Code
DAC5675A tc_pwr-fqcy1_bas334.gif Figure 5. Two-Tone IMD (Power) vs Frequency
DAC5675A tc_pwr_fqcy2_bas334.gif Figure 7. Single-Tone Spectrum Power vs Frequency
DAC5675A tc_sfdr_fo2_bas334.gif Figure 9. Spurious-Free Dynamic Range vs Frequency
DAC5675A tc_pwr-fqcy4_bas334.gif Figure 11. W-CDMA TM1 Dual Carrier Power vs Frequency
DAC5675A tc_inl-inpt_bas334.gif Figure 4. Integral Non-Linearity (INL) vs Input Code
DAC5675A tc_2imd-fi_bas334.gif Figure 6. Two-Tone IMD3 vs Frequency
DAC5675A tc_sfdr_fo1_bas334.gif Figure 8. Spurious-Free Dynamic Range vs Frequency
DAC5675A tc_pwr-fqcy3_bas334.gif Figure 10. W-CDMA TM1 Single Carrier Power vs Frequency
DAC5675A tc_aclr_fo_bas334.gif Figure 12. W-CDMA TM1 Single Carrier ACLR vs Output Frequency