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The DAC5682Z is a dual-channel 16-bit 1.0 GSPS DAC with wideband LVDS data input, integrated 2x/4x interpolation filters, onboard clock multiplier, and internal voltage reference. The DAC5682Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.
The DAC5682Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by onboard 2x or 4x FIR filters. Each interpolation FIR is configurable in either low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC5682Z | VQFN (64) | 9.00 mm × 9.00 mm |
Changes from E Revision (August 2012) to F Revision
Changes from D Revision (February 2011) to E Revision
Changes from C Revision (November 2008) to D Revision
Changes from B Revision (April 2008) to C Revision
Changes from A Revision (September 2007) to B Revision
Changes from * Revision (August 2007) to A Revision
The DAC5682Z allows both complex or real output. An optional Fs/4 coarse mixer in complex mode provides coarse frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. An external RF quadrature modulator then performs the final single sideband up-conversion. The interpolation filters and complex coarse mixers efficiently provide frequency plan flexibility while enabling higher output DAC rates to simplify image rejection filtering.
The DAC5682Z is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin QFN package. Other single-channel members of the family include the interpolating DAC5681Z and the noninterpolating DAC5681.
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
AVDD | 51, 54, 55, 59, 62 | I | Analog supply voltage. (3.3 V) | |
BIASJ | 57 | O | Full-scale output current bias. For 20-mA full-scale output current, connect a 960-Ω resistor to GND. | |
CLKIN | 2 | I | Positive external clock input with a self-bias of approximately CLKVDD/2. With the clock multiplier PLL enabled, CLKIN provides lower frequency reference clock. If the PLL is disabled, CLKIN directly provides clock for DAC up to 1 GHz. | |
CLKINC | 3 | I | Complementary external clock input. (See the CLKIN description) | |
CLKVDD | 1 | I | Internal clock buffer supply voltage. (1.8 V) | |
D[15..0]P | 7, 11, 13, 15, 17, 19, 21, 23, 27, 29, 31, 33, 35, 37, 40, 42 | I | LVDS positive input data bits 0 through 15. Each positive/negative LVDS pair has an internal 100 Ω termination resistor. Order of bus can be reversed via rev_bus bit in CONFIG5 register. Data format relative to DCLKP/N clock is Double Data Rate (DDR) with two data samples input per DCLKP/N clock. In dual-channel mode, data for the A-channel is input while DCLKP is high. | |
D15P is most significant data bit (MSB) – pin 7 D0P is least significant data bit (LSB) – pin 42 |
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D[15..0]N | 8, 12, 14, 16, 18, 20, 22, 24, 28, 30, 32, 34, 36, 38, 41, 43 | I | LVDS negative input data bits 0 through 15. (See D[15:0]P description above) | |
D15N is most significant data bit (MSB) – pin 8 D0N is least significant data bit (LSB) – pin 43 |
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DCLKP | 25 | I | LVDS positive input clock. Unlike the other LVDS inputs, the DCLKP/N pair is self-biased to approximately DVDD/2 and does not have an internal termination resistor in order to optimize operation of the DLL circuit. See DLL Operation. For proper external termination, connect a 100 Ω resistor across LVDS clock source lines followed by series 0.01 μF capacitors connected to each of DCLKP and DCLKN pins (see ). For best performance, the resistor and capacitors should be placed as close as possible to these pins. | |
DCLKN | 26 | I | LVDS negative input clock. (See the DCLKP description) | |
DVDD | 10, 39, 50, 63 | I | Digital supply voltage. (1.8 V) | |
EXTIO | 56 | I/O | Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD). Used as 1.2-V internal reference output when EXTLO = GND, requires a 0.1 μF decoupling capacitor to AGND when used as reference output. | |
EXTLO | 58 | O | Connect to GND for internal reference, or AVDD for external reference. | |
GND | 4, Thermal Pad | I | Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD and IOVDD supplies. | |
IOUTA1 | 52 | O | A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin. In single DAC mode, outputs appear on the IOUTA1/A2 pair only. | |
IOUTA2 | 53 | O | A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1 described above. An input data value of 0x0000 results in a 0-mA sink and the most positive voltage on the IOUTA2 pin. | |
IOUTB1 | 61 | O | B-Channel DAC current output. See the IOUTA1 description above. | |
IOUTB2 | 60 | O | B-Channel DAC complementary current output. See the IOUTA2 description above. | |
IOVDD | 9 | I | Digital I/O supply voltage (3.3 V) for pins RESETB, SCLK, SDENB, SDIO, SDO. | |
LPF | 64 | I | PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin may be left open. Set both PLL_bypass and PLL_sleep control bits for reduced power dissipation. | |
RESETB | 49 | I | Resets the chip when low. Internal pullup. | |
SCLK | 47 | I | Serial interface clock. Internal pulldown. | |
SDENB | 48 | I | Active low serial data enable, always an input to the DAC5682Z. Internal pullup. | |
SDIO | 46 | I/O | Bi-directional serial interface data in 3-pin mode (default). In 4-pin interface mode (CONFIG5 sif4), the SDIO pin is an input only. Internal pulldown. | |
SDO | 45 | O | Uni-directional serial interface data in 4-pin mode (CONFIG5 sif4). The SDO pin is in high-impedance state in 3-pin interface mode (default), but can optionally be used as a status output pin via CONFIG14 SDO_func_sel(2:0). Internal pulldown. | |
SYNCP | 5 | I | LVDS SYNC positive input data. The SYNCP/N LVDS pair has an internal 100 Ω termination resistor. By default, the SYNCP/N input must be logic ‘1’ to enable a DAC analog output. See the LVDS SYNCP/N Operation paragraph for a detailed description. | |
SYNCN | 6 | I | LVDS SYNC negative input data. | |
VFUSE | 44 | I | Digital supply voltage. (1.8 V) Connect to DVDD pins for normal operation. This supply pin is also used for factory fuse programming. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | DVDD(2) | –0.5 | 2.3 | V |
VFUSE(2) | –0.5 | 2.3 | V | |
CLKVDD(2) | –0.5 | 2.3 | V | |
AVDD(2) | –0.5 | 4 | V | |
IOVDD(2) | –0.5 | 4 | V | |
Supply voltage | AVDD to DVDD | –2 | 2.6 | V |
CLKVDD to DVDD | –0.5 | 0.5 | V | |
IOVDD to AVDD | –0.5 | 0.5 | V | |
D[15..0]P ,D[15..0]N, SYNCP, SYNCN (2) | –0.5 | DVDD + 0.5 | V | |
DCLKP, DCLKN(2) | –0.3 | 2.1 | V | |
CLKIN, CLKINC(2) | –0.5 | CLKVDD + 0.5 | V | |
SDO, SDIO, SCLK, SDENB, RESETB (2) | –0.5 | IOVDD + 0.5 | V | |
IOUTA1/B1, IOUTA2/B2 (2) | –0.5 | AVDD + 0.5 | V | |
LPF, EXTIO, EXTLO, BIASJ(2) | –0.5 | AVDD + 0.5 | V | |
Peak input current (any input) | 20 | mA | ||
Peak total input current (all inputs) | –30 | mA | ||
Operating free-air temperature, TA: DAC5682Z | –40 | 85 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | |
---|---|---|---|---|
SUPPLIES | ||||
AVDD | 3 | 3.3 | 3.6 | V |
DVDD | 1.7 | 1.8 | 1.9 | V |
CLKVDD | 1.7 | 1.8 | 1.9 | V |
IOVDD | 3 | 3.3 | 3.6 | V |
ANALOG OUTPUT | ||||
IOUTA1, IOUTA2, IOUTB1, IOUTB2 | 0 | 20 | 20 | mA |
V IOUTA1, IOUTA2, IOUTB1, IOUTB2 Compliance voltage | AVDD-0.5 | AVDD+0.5 | V | |
CLOCK INPUT | ||||
CLKIN ECL/PECL Frequency | 1000 | MHz | ||
CLKIN Amplitude Differential | 0.4 | 1 | CLKVDD | V |
CLKIN Duty Cycle | 50% | |||
CLKIN common mode voltage | CLKDVDD/2 | V | ||
DCLK LVDS Frequency | 500 | MHz | ||
DIGITAL INPUTS | ||||
SYNC LVDS | 1 | 1.2 | 1.4 | V |
D15..D0 LVDS | 1 | 1.2 | 1.4 | V |
LVDS Common mode | 1.2 | V | ||
LVDS Differential Swing | 0.4 | V | ||
SCLK, SDIO, SDENB, SDO CMOS SPI | GND | IOVDD | V |
THERMAL METRIC(1) | DAC5682Z | UNIT | |
---|---|---|---|
QFN | |||
64 PINS | |||
TJ | Maximum junction temperature (2) | 125 | °C |
RθJA | Theta junction-to-ambient (still air) | 22 | °C/W |
Theta junction-to-ambient (150 lfm) | 16 | ||
RθJC | Theta junction-to-case | 0.2 | °C/W |
RθJP | Theta junction-to-pad | 3.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Resolution | 16 | Bits | ||||
DC ACCURACY(1) | ||||||
INL | Integral nonlinearity | 1 LSB = IOUTFS/216 | ±4 | LSB | ||
DNL | Differential nonlinearity | ±2 | ||||
ANALOG OUTPUT | ||||||
Course gain linearity | ±0.04 | LSB | ||||
Offset error | Mid code offset | 0.01 | %FSR | |||
Gain error | With external reference | 1 | %FSR | |||
Gain error | With internal reference | 0.7 | %FSR | |||
Gain mismatch | With internal reference, dual DAC | –2 | 2 | %FSR | ||
Minimum full scale output current(2) | 2 | mA | ||||
Maximum full scale output current(2) | 20 | |||||
Output Compliance range(3) | IOUTFS = 20 mA | AVDD –0.5V |
AVDD + 0.5V |
V | ||
Output resistance | 300 | kΩ | ||||
Output capacitance | 5 | pF | ||||
REFERENCE OUTPUT | ||||||
Vref | Reference voltage | 1.14 | 1.2 | 1.26 | V | |
Reference output current(4) | 100 | nA | ||||
REFERENCE INPUT | ||||||
VEXTIO | Input voltage range | 0.1 | 1.25 | V | ||
Input resistance | 1 | MΩ | ||||
Small signal bandwidth | CONFIG6: BiasLPF_A and BiasLPF_B = 0 | 95 | kHz | |||
CONFIG6: BiasLPF_A and BiasLPF_B = 1 | 472 | |||||
Input capacitance | 100 | pF | ||||
TEMPERATURE COEFFICIENTS | ||||||
Offset drift | ±1 | ppm of FSR/°C | ||||
Gain drift | With external reference | ±15 | ppm of FSR/°C | |||
With internal reference | ±30 | |||||
Reference voltage drift | ±8 | ppm/°C | ||||
POWER SUPPLY | ||||||
Analog supply voltage, AVDD | 3.0 | 3.3 | 3.6 | V | ||
Digital supply voltage, DVDD | 1.7 | 1.8 | 1.9 | V | ||
Clock supply voltage, CLKVDD | 1.7 | 1.8 | 1.9 | V | ||
I/O supply voltage, IOVDD | 3.0 | 3.3 | 3.6 | V | ||
I(AVDD) | Analog supply current | Mode 4 (below) | 133 | mA | ||
I(DVDD) | Digital supply current | 455 | mA | |||
I(CLKVDD) | Clock supply current | 45 | mA | |||
I(IOVDD) | IO supply current | 12 | mA | |||
I(AVDD) | Sleep mode, AVDD supply current | Mode 6 (below) | 1.0 | mA | ||
I(DVDD) | Sleep mode, DVDD supply current | 1.5 | mA | |||
I(CLKVDD) | Sleep mode, CLKVDD supply current | 2.5 | mA | |||
I(IOVDD) | Sleep mode, IOVDD supply current | 2.0 | mA | |||
P | AVDD + IOVDD current, 3.3 V | Mode 1: 2X2, PLL = OFF, CLKIN = 983.04 MHz FDAC = 983.04 MHz, IF = 184.32 MHz DACA and DACB ON, 4 carrier WCDMA |
135 | mA | ||
DVDD + CLKVDD current, 1.8 V | 450 | mA | ||||
Power Dissipation | 1255 | mW | ||||
AVDD + IOVDD current, 3.3 V | Mode 2: 2X2, PLL = ON (8X), CLKIN = 122.88 MHz FDAC = 983.04 MHz, IF = 184.32 MHz DACA and DACB ON, 4 carrier WCDMA |
145 | mA | |||
DVDD + CLKVDD current, 1.8 V | 485 | mA | ||||
Power Dissipation | 1350 | mW | ||||
AVDD + IOVDD current, 3.3 V | Mode 3: 2X4, CMIX0 = Fs/4, PLL = OFF, CLKIN = 983.04 MHz FDAC = 983.04 MHz, IF = 215.04 MHz DACA and DACB ON, 4 carrier WCDMA |
135 | mA | |||
DVDD + CLKVDD current, 1.8 V | 480 | mA | ||||
Power Dissipation | 1310 | mW | ||||
AVDD + IOVDD current, 3.3 V | Mode 4: 2X4, CMIX0 = Fs/4, PLL = ON (8X), CLKIN = 122.88 MHz FDAC = 983.04 MHz, IF = 215.04 MHz DACA and DACB ON, 4 carrier WCDMA |
145 | mA | |||
DVDD + CLKVDD current, 1.8 V | 505 | mA | ||||
Power Dissipation | 1400 | 1600 | mW | |||
AVDD + IOVDD current, 3.3 V | Mode 5: 2X2, CMIX0 = Fs/4, PLL = OFF, CLKIN = 983.04 MHz FDAC = 983.04 MHz, Digital Logic Disabled DACA and DACB SLEEP, Static Data Pattern |
5 | mA | |||
DVDD + CLKVDD current, 1.8 V | 185 | mA | ||||
Power Dissipation | 350 | mW | ||||
AVDD + IOVDD current, 3.3 V | Mode 6: 2X4, PLL = OFF, CLKIN = OFF FDAC = OFF, Digital Logic Disabled DACA and DACB = SLEEP, Static Data Pattern |
3.0 | mA | |||
DVDD + CLKVDD current, 1.8 V | 4.0 | mA | ||||
Power Dissipation | 17.0 | 30.0 | mW | |||
PSRR | Power supply rejection ratio | DC tested | –0.2 | 0.2 | %FSR/V | |
T | Operating range | –40 | 85 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG OUTPUT | ||||||
fCLK | Maximum output update rate | 1000 | MSPS | |||
ts(DAC) | Output settling time to 0.1% | Transition: Code 0x0000 to 0xFFFF | 10.4 | ns | ||
tpd | Output propagation delay | 2.5 | ns | |||
tr(IOUT) | Output rise time 10% to 90% | 220 | ps | |||
tf(IOUT) | Output fall time 90% to 10% | 220 | ps | |||
Digital latency | No interpolation, PLL Off | 78 | DAC clock cycles | |||
x2 interpolation, PLL Off | 163 | |||||
x4 interpolation, PLL Off | 308 | |||||
Power-up time | DAC wake-up time | IOUT current settling to 1% of IOUTFS. Measured from SDENB; Register 0x06, toggle Bit 4 from 1 to 0. |
80 | μs | ||
DAC sleep time | IOUT current settling to 1% of IOUTFS. Measured from SDENB; Register 0x06, toggle Bit 4 from 0 to 1. |
80 | ||||
AC PERFORMANCE | ||||||
SFDR | Spurious free dynamic range | 1X1, PLL off, CLKIN = 500 MHz, DACA on, IF = 5.1 MHz, First Nyquist Zone < fDATA/2 |
81 | dBc | ||
2X2, PLL off, CLKIN = 1000 MHz, DACA and DACB on, IF = 5.1 MHz, First Nyquist Zone < fDATA/2 |
80 | |||||
2X2, PLL off, CLKIN = 1000 MHz, DACA and DACB on, IF = 20.1 MHz, First Nyquist Zone < fDATA/2 |
77 | |||||
SNR | Signal-to-noise ratio | 2X2, PLL off, CLKIN = 500 MHZ, DACA and DACB on, Single tone, 0 dBFS, IF = 20.1 MHz | 75 | dBc | ||
2X2, PLL off, CLKIN = 1000 MHZ, DACA and DACB on, Single tone, 0 dBFS, IF = 20.1 MHz | 70 | |||||
2X2, PLL off, CLKIN = 1000 MHZ, DACA and DACB on, Single tone, 0 dBFS, IF = 70.1 MHz | 66 | |||||
2X4, PLL off, CLKIN = 1000 MHZ, DACA and DACB on, Single tone, 0 dBFS, IF = 180 MHz | 60 | |||||
2X2 CMIX, PLL off, CLKIN = 1000 MHZ, DACA and DACB on, Single tone, 0 dBFS, IF = 300.2 MHz | 60 | |||||
2X2, PLL off, CLKIN = 1000 MHZ, DACA and DACB on, Four tone, each -12 dBFS, IF = 24.7, 24.9, 25.1 and 25.3 MHz | 73 | |||||
IMD3 | Third-order two-tone intermodulation (each tone at –6 dBFS) |
2X2, PLL off, CLKIN = 1000 MHZ, DACA and DACB on, IF = 20.1 and 21.1 MHz |
88 | dBc | ||
2X2, PLL off, CLKIN = 1000 MHZ, DACA and DACB on, IF = 70.1 and 71.1 MHz |
75 | |||||
2X2 CMIX, PLL off, CLKIN = 1000 MHZ, DACA and DACB on, IF = 150.1 and 151.1 MHz |
67 | |||||
IMD | Four-tone intermodulation (each tone at –12 dBFS) | 2X2 CMIX, PLL off, CLKIN = 1000 MHz, DACA and DACB on, fOUT = 298.4, 299.2, 300.8 and 301.6 MHz |
64 | dBc | ||
ACLR(2) | Adjacent channel leakage ratio | Single carrier, baseband, 2X2, PLL off, CLKIN = 983.04 MHz, DACA and DACB on | 80 | 83 | dBc | |
Single carrier, IF = 180 MHz, 2X2, PLL off, CLKIN = 983.04 MHz, DACA and DACB on |
73 | |||||
Four carrier, IF = 180 MHz, 2X2 CMIX, PLL off, CLKIN = 983.04 MHz, DACA and DACB on |
68 | |||||
Four carrier, IF = 275 MHz, 2X2 CMIX, PLL off, CLKIN = 983.04 MHz, DACA and DACB on |
66 | |||||
Noise floor(3) | 50-MHz offset, 1-MHz BW, Single Carrier, baseband, 2X2, PLL off, CLKIN = 983.04 | 93 | dBc | |||
50-MHz offset, 1-MHz BW, Four Carrier, baseband, 2X2, PLL off, CLKIN = 983.04. | 85 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
LVDS INTERFACE: D[15:0]P/N, SYNCP/N, DCLKP/N(1) | ||||||||
VA,B+ | Logic high differential input voltage threshold | 175 | mV | |||||
VA,B– | Logic low differential input voltage threshold | –175 | mV | |||||
VCOM1 | Input Common Mode | SYNCP/N, D[15:0]P/N only | 1.0 | V | ||||
VCOM2 | Input Common Mode | DCLKP/N only | DVDD ÷2 |
V | ||||
ZT | Internal termination | SYNCP/N, D[15:0]P/N only | 85 | 110 | 135 | Ω | ||
CL | LVDS Input capacitance | 2 | pF | |||||
tS, tH | DCLK to Data | DCLKP/N: 0 to 125 MHz (see Figure 43) DLL Disabled, CONFIG5 DLL_bypass = 1, CONFIG10 = '00000000' | Setup_min | 1100 | ps | |||
Hold_min | –600 | |||||||
tSKEW(A), tSKEW(B) | DCLK to Data Skew(2)
|
DLL Enabled, CONFIG5 DLL_bypass = 0, DDR format |
DCLKP/N = 150 MHz | Positive | 1000 | ps | ||
Negative | –1800 | |||||||
DCLKP/N = 200 MHz | Positive | 800 | ||||||
Negative | –1300 | |||||||
DCLKP/N = 250 MHz | Positive | 600 | ||||||
Negative | –1000 | |||||||
DCLKP/N = 300 MHz | Positive | 450 | ||||||
Negative | –800 | |||||||
DCLKP/N = 350 MHz | Positive | 400 | ||||||
Negative | –700 | |||||||
DCLKP/N = 400 MHz | Positive | 300 | ||||||
Negative | –600 | |||||||
DCLKP/N = 450 MHz | Positive | 300 | ||||||
Negative | –500 | |||||||
DCLKP/N = 500 MHz | Positive | 350 | ||||||
Negative | –300 | |||||||
fDATA | Input data rate supported |
DLL Disabled, CONFIG5 DLL_bypass = 1, DDR format, DCLKP frequency: <125 MHz |
250 | MSPS | ||||
DLL Enabled, CONFIG5 DLL_bypass = 0, DDR format, DCLKP frequency: 125 to 500 MHz |
250 | 1000 | ||||||
DLL Operating Frequency (DCLKP/N Frequency) | DLL Enabled, CONFIG5 DLL_bypass = 0, DDR format |
CONFIG10 = '11001101' = 0xCD | 125 | 150 | MHz | |||
CONFIG10 = '11001110' = 0xCE | 150 | 175 | ||||||
CONFIG10 = '11001111' = 0xCF | 175 | 200 | ||||||
CONFIG10 = '11001000' = 0xC8 | 200 | 325 | ||||||
CONFIG10 = '11000000' = 0xC0 | 325 | 500 | ||||||
CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB | ||||||||
VIH | High-level input voltage | 2 | 3 | V | ||||
VIL | Low-level input voltage | 0 | 0 | 0.8 | V | |||
IIH | High-level input current | ±20 | μA | |||||
IIL | Low-level input current | ±20 | μA | |||||
CI | CMOS Input capacitance | 5 | pF | |||||
VOH | SDO, SDIO | Iload = –100 μA | IOVDD –0.2 |
V | ||||
Iload = –2 mA | 0.8 x IOVDD |
V | ||||||
VOL | SDO, SDIO | Iload = 100 μA | 0.2 | V | ||||
Iload = 2 mA | 0.5 | V | ||||||
ts(SDENB) | Setup time, SDENB to rising edge of SCLK | 20 | ns | |||||
ts(SDIO) | Setup time, SDIO valid to rising edge of SCLK | 10 | ns | |||||
th(SDIO) | Hold time, SDIO valid to rising edge of SCLK | 5 | ns | |||||
t(SCLK) | Period of SCLK | 100 | ns | |||||
t(SCLKH) | High time of SCLK | 40 | ns | |||||
t(SCLKL) | Low time of SCLK | 40 | ns | |||||
td(Data) | Data output delay after falling edge of SCLK | 10 | ns | |||||
tRESET | Minimum RESETB pulse width | 25 | ns | |||||
CLOCK INPUT (CLKIN/CLKINC) | ||||||||
Duty cycle | 50% | |||||||
Differential voltage(3) | 0.4 | 1 | V | |||||
CLKIN/CLKINC input common mode | CLKVDD ÷2 |
V | ||||||
PHASE LOCKED LOOP | ||||||||
Phase noise | DAC output at 600 kHz offset, 100 MHz, 0-dBFS tone, 2X4, fDATA = 250 MSPS, CLKIN/C = 250 MHz, PLL_m = '00111', PLL_n = '001', VCO_div2 = 0, PLL_range = '1111', PLL_gain = '00' |
–125 | dBc/ Hz | |||||
DAC output at 6 MHz offset, 100 MHz, 0-dBFS tone, 2X4, fDATA = 250 MSPS, CLKIN/C = 250 MHz, PLL_m = '00111', PLL_n = '001', VCO_div2 = 0, PLL_range = '1111', PLL_gain = '00' |
–146 | |||||||
PLL/VCO Operating Frequency, Typical VCO Gain |
PLL_gain = '00', PLL_range = '0000' (0) | 160 | 290 | MHz | ||||
220 | MHz/V | |||||||
PLL_gain = '01', PLL_range = '0001' (1) | 290 | 460 | MHz | |||||
300 | MHz/V | |||||||
PLL_gain = '01', PLL_range = '0010' (2) | 400 | 520 | MHz | |||||
260 | MHz/V | |||||||
PLL_gain = '01', PLL_range = '0011' (3) | 480 | 570 | MHz | |||||
240 | MHz/V | |||||||
PLL_gain = '01', PLL_range = '0100' (4) | 560 | 620 | MHz | |||||
210 | MHz/V | |||||||
PLL_gain = '10', PLL_range = '0101' (5) | 620 | 740 | MHz | |||||
270 | MHz/V | |||||||
PLL_gain = '10', PLL_range = '0110' (6) | 690 | 780 | MHz | |||||
250 | MHz/V | |||||||
PLL_gain = '10', PLL_range = '0111' (7) | 740 | 820 | MHz | |||||
240 | MHz/V | |||||||
PLL_gain = '10', PLL_range = '1000' (8) | 790 | 850 | MHz | |||||
220 | MHz/V | |||||||
PLL_gain = '10', PLL_range = '1001' (9) | 840 | 880 | MHz | |||||
210 | MHz/V | |||||||
PLL_gain = '11', PLL_range = '1010' (A) | 880 | 940 | MHz | |||||
250 | MHz/V | |||||||
PLL_gain = '11', PLL_range = '1011' (B) | 920 | 990 | MHz | |||||
230 | MHz/V | |||||||
PLL_gain = '11', PLL_range = '1100' (C) | 960 | 1000 | MHz | |||||
220 | MHz/V | |||||||
PFD Maximum Frequency | 160 | MHz |