JAJSE83D April   2016  – December 2017 DAC60004 , DAC70004 , DAC80004

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 DACx0004 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Amplifier
      2. 8.3.2 Reference Buffer
      3. 8.3.3 Power-On Reset
        1. 8.3.3.1 POR Pin Feature
        2. 8.3.3.2 Internal Power-On Reset (IPOR) Levels
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface
        1. 8.4.1.1 Stand-Alone Mode
          1. 8.4.1.1.1 SYNC Interrupt - Stand-Alone Mode
          2. 8.4.1.1.2 Read-Back Mode
        2. 8.4.1.2 Daisy-Chain Mode
          1. 8.4.1.2.1 SYNC Interrupt - Daisy-Chain Mode
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 DAC Power-Down Modes
      4. 8.4.4 CLR Pin Functionality and Software CLEAR Mode
        1. 8.4.4.1 DAC Clear Mode Registers
      5. 8.4.5 LDAC Pin Functionality
        1. 8.4.5.1 Software LDAC Mode Registers
      6. 8.4.6 Software Reset Mode
      7. 8.4.7 Output Short Circuit Limit Register
      8. 8.4.8 Status Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Digitally Controlled Asymmetric Bipolar Output
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. As a general rule it is important to keep digital traces as far away from analog traces when possible.

The DACx0004 is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output.

Due to the single ground pin of the DACx0004, all return currents, including digital and analog return currents for the DAC, must flow through a single point. Ideally, GND must be connected directly to an analog ground plane. This plane must be separate from the ground connection for the digital components until they were connected at the power-entry point of the system.

As with the GND connection, VDD should be connected to a 5 V power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. It is recommended to have an additional 1 μF to 10 μF capacitor and 0.1 μF bypass capacitor. In some situations, additional bypassing may be required, such as a 100 μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5 V supply, removing the high-frequency noise. In general it is always a good idea to maintain the digital signals away from analog signals.

11.2 Layout Example

DAC80004 DAC70004 DAC60004 layoutexample_slase44.png Figure 60. Layout Diagram