JAJSI90A November   2019  – April 2020 DAC60502 , DAC70502 , DAC80502

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Requirements : SPI Mode
    7. 8.7  Timing Requirements : I2C Standard Mode
    8. 8.8  Timing Requirements : I2C Fast Mode
    9. 8.9  Timing Requirements : I2C Fast-Mode Plus
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 9.3.1.1 DAC Transfer Function
        2. 9.3.1.2 DAC Register Structure
        3. 9.3.1.3 Output Amplifier
      2. 9.3.2 Internal Reference
        1. 9.3.2.1 Solder Heat Reflow
      3. 9.3.3 Power-On Reset (POR)
      4. 9.3.4 Software Reset
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 SPI Mode
          1. 9.5.1.1.1 SYNC Interrupt
        2. 9.5.1.2 I2C Mode
          1. 9.5.1.2.1 F/S Mode Protocol
          2. 9.5.1.2.2 DACx0502 I2C Update Sequence
            1. 9.5.1.2.2.1 DACx0502 Address Byte
            2. 9.5.1.2.2.2 DACx0502 Command Byte
            3. 9.5.1.2.2.3 DACx0502 Data Byte (MSDB and LSDB)
          3. 9.5.1.2.3 DACx0502 I2C Read Sequence
    6. 9.6 Register Maps
      1. 9.6.1 Registers
        1. 9.6.1.1 NOOP Register (offset = 0h) [reset = 0000h]
          1. Table 9. NOOP Register Field Descriptions
        2. 9.6.1.2 DEVID Register (offset = 1h) [reset = 0214h for DAC80502, 1214h for DAC70502, 2214h for DAC60502]
          1. Table 10. DEVID Register Field Descriptions
        3. 9.6.1.3 SYNC Register (offset = 2h) [reset = 0300h]
          1. Table 11. SYNC Register Field Descriptions
        4. 9.6.1.4 CONFIG Register (offset = 3h) [reset = 0000h]
          1. Table 12. CONFIG Register Field Descriptions
        5. 9.6.1.5 GAIN Register (offset = 4h) [reset = 0003h]
          1. Table 13. GAIN Register Field Descriptions
        6. 9.6.1.6 TRIGGER Register (offset = 5h) [reset = 0000h]
          1. Table 14. TRIGGER Register Field Descriptions
        7. 9.6.1.7 BRDCAST Register (offset = 6h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
          1. Table 15. BRDCAST Register Field Descriptions
        8. 9.6.1.8 STATUS Register (offset = 7h) [reset = 0000h]
          1. Table 16. STATUS Register Field Descriptions
        9. 9.6.1.9 DAC-n Register (offset = 8h–9h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
          1. Table 17. DAC-A Data Register Field Descriptions (8h)
          2. Table 18. DAC-B Data Register Field Descriptions (9h)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 SPI Connection to a Processor
      2. 10.3.2 I2C Interface Connection to a Processor
    4. 10.4 What To Do and What Not To Do
      1. 10.4.1 What To Do
      2. 10.4.2 What Not To Do
    5. 10.5 Initialization Setup
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.5.1.2.1 F/S Mode Protocol

  1. The master initiates data transfer by generating a start condition. The start condition is when a high to-low transition occurs on the SDA line while SCL is high, as shown in Figure 60. All I2C-compatible devices recognize a start condition.
    2. DAC80502 DAC70502 DAC60502 SBAS793_DACx0502_STRTSTP_CONDT.gifFigure 60. Start and Stop Conditions
    DAC80502 DAC70502 DAC60502 SBAS793_DACx0502_Bit_Trnsfer.gifFigure 61. Bit Transfer on the I2C Bus
  2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit (R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in Figure 61. All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge by pulling the SDA line low during the entire high period of the 9th SCL cycle, as shown in Figure 59. Upon detecting this acknowledge, the master knows the communication link with a slave has been established.
  3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In either case, the receiver must acknowledge the data sent by the transmitter so that the acknowledge signal can be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consists of eight data bits and one acknowledge-bit, and can continue for as long as necessary.
  4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low-to-high while the SCL line is high (see Figure 60). This action releases the bus and stops the communication link with the addressed slave. All I2C-compatible devices recognize the stop condition. Upon receipt of a stop condition, the bus is released, and all slave devices then wait for a start condition followed by a matching address.