JAJSFQ0A July 2018 – November 2018 DAC61408 , DAC71408 , DAC81408
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
SERIAL INTERFACE - WRITE OPERATION | ||||||
f(SCLK) | Serial clock frequency | VIO = 1.7 V to 2.7 V | 25 | MHz | ||
VIO = 2.7 V to 5.5 V | 50 | |||||
tSCLKHIGH | SCLK high time | VIO = 1.7 V to 2.7 V | 20 | ns | ||
VIO = 2.7 V to 5.5 V | 10 | |||||
tSCLKLOW | SCLK low time | VIO = 1.7 V to 2.7 V | 20 | ns | ||
VIO = 2.7 V to 5.5 V | 10 | |||||
tSDIS | SDI setup time | VIO = 1.7 V to 2.7 V | 10 | ns | ||
VIO = 2.7 V to 5.5 V | 5 | |||||
tSDIH | SDI hold time | VIO = 1.7 V to 2.7 V | 10 | ns | ||
VIO = 2.7 V to 5.5 V | 5 | |||||
tCSS | CS to SCLK falling edge setup time | VIO = 1.7 V to 2.7 V | 30 | ns | ||
VIO = 2.7 V to 5.5 V | 15 | |||||
tCSH | SCLK falling edge to CS rising edge | VIO = 1.7 V to 2.7 V | 10 | ns | ||
VIO = 2.7 V to 5.5 V | 5 | |||||
tCSHIGH | CS hight time | VIO = 1.7 V to 2.7 V | 50 | ns | ||
VIO = 2.7 V to 5.5 V | 25 | |||||
tDACWAIT | Sequential DAC update wait time | VIO = 1.7 V to 2.7 V | 2.4 | µs | ||
VIO = 2.7 V to 5.5 V | 2.4 | |||||
tBCASTWAIT | Broadcast DAC update wait time | VIO = 1.7 V to 2.7 V | 4 | µs | ||
VIO = 2.7 V to 5.5 V | 4 | |||||
SERIAL INTERFACE - READ AND DAISY CHAIN OPERATION, FSDO = 0 | ||||||
f(SCLK) | Serial clock frequency | VIO = 1.7 V to 2.7 V | 15 | MHz | ||
VIO = 2.7 V to 5.5 V | 20 | |||||
tSCLKHIGH | SCLK high time | VIO = 1.7 V to 2.7 V | 33 | ns | ||
VIO = 2.7 V to 5.5 V | 25 | |||||
tSCLKLOW | SCLK low time | VIO = 1.7 V to 2.7 V | 33 | ns | ||
VIO = 2.7 V to 5.5 V | 25 | |||||
tSDIS | SDI setup time | VIO = 1.7 V to 2.7 V | 10 | ns | ||
VIO = 2.7 V to 5.5 V | 5 | |||||
tSDIH | SDI hold time | VIO = 1.7 V to 2.7 V | 10 | ns | ||
VIO = 2.7 V to 5.5 V | 5 | |||||
tCSS | CS to SCLK falling edge setup time | VIO = 1.7 V to 2.7 V | 30 | ns | ||
VIO = 2.7 V to 5.5 V | 20 | |||||
tCSH | SCLK falling edge to CS rising edge | VIO = 1.7 V to 2.7 V | 8 | ns | ||
VIO = 2.7 V to 5.5 V | 5 | |||||
tCSHIGH | CS high time | VIO = 1.7 V to 2.7 V | 50 | ns | ||
VIO = 2.7 V to 5.5 V | 25 | |||||
tSDOZD | SDO tri-state to driven | VIO = 1.7 V to 2.7 V | 0 | 20 | ns | |
VIO = 2.7 V to 5.5 V | 0 | 20 | ||||
tSDODLY | SDO output delay | VIO = 1.7 V to 2.7 V | 0 | 35 | ns | |
VIO = 2.7 V to 5.5 V | 0 | 20 | ||||
SERIAL INTERFACE - READ AND DAISY CHAIN OPERATION, FSDO = 1 | ||||||
f(SCLK) | Serial clock frequency | VIO = 1.7 V to 2.7 V | 25 | MHz | ||
VIO = 2.7 V to 5.5 V | 35 | |||||
tSCLKHIGH | SCLK high time | VIO = 1.7 V to 2.7 V | 20 | ns | ||
VIO = 2.7 V to 5.5 V | 14 | |||||
tSCLKLOW | SCLK low time | VIO = 1.7 V to 2.7 V | 20 | ns | ||
VIO = 2.7 V to 5.5 V | 14 | |||||
tSDIS | SDI setup time | VIO = 1.7 V to 2.7 V | 10 | ns | ||
VIO = 2.7 V to 5.5 V | 5 | |||||
tSDIH | SDI hold time | VIO = 1.7 V to 2.7 V | 10 | ns | ||
VIO = 2.7 V to 5.5 V | 5 | |||||
tCSS | CS to SCLK falling edge setup time | VIO = 1.7 V to 2.7 V | 30 | ns | ||
VIO = 2.7 V to 5.5 V | 20 | |||||
tCSH | SCLK falling edge to CS rising edge | VIO = 1.7 V to 2.7 V | 8 | ns | ||
VIO = 2.7 V to 5.5 V | 5 | |||||
tCSHIGH | CS high time | VIO = 1.7 V to 2.7 V | 50 | ns | ||
VIO = 2.7 V to 5.5 V | 25 | |||||
tSDOZD | SDO tri-state to driven | VIO = 1.7 V to 2.7 V | 0 | 20 | ns | |
VIO = 2.7 V to 5.5 V | 0 | 20 | ||||
tSDODLY | SDO output delay | VIO = 1.7 V to 2.7 V | 0 | 35 | ns | |
VIO = 2.7 V to 5.5 V | 0 | 20 | ||||
DIGITAL LOGIC | ||||||
tLOGDLY | CS rising edge to LDAC or CLR falling edge delay time | VIO = 1.7 V to 2.7 V | 40 | ns | ||
tLOGDLY | CS rising edge to LDAC or CLR falling edge delay time | VIO = 2.7 V to 5.5 V | 20 | |||
tLDAC | LDAC low time | VIO = 1.7 V to 2.7 V | 20 | ns | ||
VIO = 2.7 V to 5.5 V | 10 | |||||
tCLR | CLR low time | VIO = 1.7 V to 2.7 V | 20 | ns | ||
VIO = 2.7 V to 5.5 V | 10 | |||||
tRESET | POR reset delay | VIO = 1.7 V to 2.7 V | 1 | ms | ||
VIO = 2.7 V to 5.5 V | 1 | |||||
fTOGGLE | TOGGLE frequency | VIO = 1.7 V to 2.7 V | 100 | kHz | ||
VIO = 2.7 V to 5.5 V | 100 |