JAJSFQ0A
July 2018 – November 2018
DAC61408
,
DAC71408
,
DAC81408
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
機能ブロック図
4
改訂履歴
5
概要(続き)
6
Device Comparison Table
7
Pin Configuration and Functions
Pin Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Parameter Measurement Information
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Digital-to-Analog Converters (DACs) Architecture
10.3.1.1
DAC Transfer Function
10.3.1.2
DAC Register Structure
10.3.1.2.1
DAC Register Synchronous and Asynchronous Updates
10.3.1.2.2
Broadcast DAC Register
10.3.1.2.3
Clear DAC Operation
10.3.2
Internal Reference
10.3.3
Device Reset Options
10.3.3.1
Power-on-Reset (POR)
10.3.3.2
Hardware Reset
10.3.3.3
Software Reset
10.3.4
Thermal Protection
10.3.4.1
Analog Temperature Sensor: TEMPOUT Pin
10.3.4.2
Thermal Shutdown
10.4
Device Functional Modes
10.4.1
Toggle Mode
10.4.2
Differential Mode
10.4.3
Power-Down Mode
10.5
Programming
10.5.1
Stand-Alone Operation
10.5.1.1
Streaming Mode Operation
10.5.2
Daisy-Chain Operation
10.5.3
Frame Error Checking
10.6
Register Maps
10.6.1
NOP Register (Offset = 00h) [reset = 0000h]
Table 9.
NOP Register Field Descriptions
10.6.2
DEVICEID Register (Offset = 01h) [reset = ----h]
Table 10.
DEVICEID Register Field Descriptions
10.6.3
STATUS Register (Offset = 02h) [reset = 0000h]
Table 11.
STATUS Register Field Descriptions
10.6.4
SPICONFIG Register (Offset = 03h) [reset = 0A24h]
Table 12.
SPICONFIG Register Field Descriptions
10.6.5
GENCONFIG Register (Offset = 04h) [reset = 7F00h]
Table 13.
GENCONFIG Register Field Descriptions
10.6.6
BRDCONFIG Register (Offset = 05h) [reset = FFFFh]
Table 14.
BRDCONFIG Register Field Descriptions
10.6.7
SYNCCONFIG Register (Offset = 06h) [reset = 0000h]
Table 15.
SYNCCONFIG Register Field Descriptions
10.6.8
TOGGCONFIG0 Register (Offset = 07h) [reset = 0000h]
Table 16.
TOGGCONFIG0 Register Field Descriptions
10.6.9
TOGGCONFIG1 Register (Offset = 08h) [reset = 0000h]
Table 17.
TOGGCONFIG1 Register Field Descriptions
10.6.10
DACPWDWN Register (Offset = 09h) [reset = FFFFh]
Table 18.
DACPWDWN Register Field Descriptions
10.6.11
DACRANGEn Register (Offset = 0Bh - 0Ch) [reset = 0000h]
Table 19.
DACRANGEn Register Field Descriptions
10.6.12
TRIGGER Register (Offset = 0Eh) [reset = 0000h]
Table 20.
TRIGGER Register Field Descriptions
10.6.13
BRDCAST Register (Offset = 0Fh) [reset = 0000h]
Table 21.
BRDCAST Register Field Descriptions
10.6.14
DACn Register (Offset = 14h - 1Bh) [reset = 0000h]
Table 22.
DACn Register Field Descriptions
10.6.15
OFFSETn Register (Offset = 21h - 22h) [reset = 0000h]
Table 23.
OFFSETn Register Field Descriptions
11
Application and Implementation
11.1
Application Information
11.2
Typical Application
11.2.1
Design Requirements
11.2.2
Detailed Design Procedure for Remote Ground Tracking
11.2.2.1
Generating 300mV Offset
11.2.2.2
Amplifier Selection
11.2.2.3
Passive Component Selection
11.2.3
Application Curves
12
Power Supply Recommendations
13
Layout
13.1
Layout Guidelines
13.2
Layout Example
14
デバイスおよびドキュメントのサポート
14.1
ドキュメントのサポート
14.2
関連リンク
14.3
ドキュメントの更新通知を受け取る方法
14.4
コミュニティ・リソース
14.5
商標
14.6
静電気放電に関する注意事項
14.7
Glossary
15
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHA|40
MPQF135D
サーマルパッド・メカニカル・データ
RHA|40
QFND650
発注情報
jajsfq0a_oa
jajsfq0a_pm
10.3
Feature Description