JAJSFQ0A July 2018 – November 2018 DAC61408 , DAC71408 , DAC81408
PRODUCTION DATA.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
OUT[0:7] | 5 - 8, 23 - 26 | O | Analog DAC output voltages. |
NC | 1, 2, 3, 4, 27, 28, 29, 30 | O | No connection. |
VIO | 9 | PWR | IO supply voltage. (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the device. |
GND | 10, 36 | GND | Ground reference point for all circuitry on the device. |
SDO | 11 | O | Serial interface data output. The SDO pin must be enabled before operation by setting the SDO-EN bit. Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by the FSDO bit (rising edge by default). |
SCLK | 12 | I | Serial interface clock. |
SDI | 13 | I | Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK pin. |
CS | 14 | I | Active low serial data enable. This input is the frame synchronization signal for the serial data. When the signal goes low, it enables the serial interface input shift register. |
TOGGLE0 | 15 | I | Toggle pins. Control signals for those DAC outputs configured for toggle operation to switch between the two DAC data registers associated with each DAC. A logic low updates the DAC output to the value set by Register A. A logic high updates the DAC output to the value set by Register B. Connect the TOGGLE pins to ground if not using the toggle operation. |
TOGGLE1 | 16 | I | |
TOGGLE2 | 17 | I | |
LDAC | 18 | I | Active low synchronization signal. When the LDAC pin is low, the DAC outputs of those channels configured in synchronous mode are updated simultaneously. Connect to VIO if unused. |
RESET | 19 | I | Active low reset input. Logic low on this pin causes the device to issue a power-on-reset event. |
CLR | 20 | I | Active low clear input. Logic low on this pin clears all DAC outputs to their clear code. Connect to VIO if unused. |
ALMOUT | 21 | O | ALMOUT is an open drain alarm output. An external 10-kΩ pull-up resistor to a voltage no higher than VIO is required. |
TEMPOUT | 22 | O | Analog temperature monitor output. |
VCC | 31, 40 | PWR | Output positive analog power supply (9 V to 41.5 V). |
VSS | 32, 39 | PWR | Output negative analog power supply (-21.5 V to 0 V). |
REF | 33 | I/O | Reference input to the device when operating with external reference. When using internal reference, this is the reference output voltage pin. Connect a 150-nF capacitor to ground. |
REFCMP | 34 | I/O | Reference compensation capacitor connection. Connect a 330-pF capacitor between REFCMP and REFGND. |
REFGND | 35 | GND | Ground reference point for the internal reference. |
VAA | 37 | PWR | Analog supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VDD pin. |
VDD | 38 | PWR | Digital supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VAA pin. |
THERMAL PAD | – | – | The thermal pad is located on the package underside. The thermal pad should be connected to any internal PCB ground plane through multiple vias for good thermal performance. |