JAJSFQ0A July   2018  – November 2018 DAC61408 , DAC71408 , DAC81408

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Digital-to-Analog Converters (DACs) Architecture
        1. 10.3.1.1 DAC Transfer Function
        2. 10.3.1.2 DAC Register Structure
          1. 10.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 10.3.1.2.2 Broadcast DAC Register
          3. 10.3.1.2.3 Clear DAC Operation
      2. 10.3.2 Internal Reference
      3. 10.3.3 Device Reset Options
        1. 10.3.3.1 Power-on-Reset (POR)
        2. 10.3.3.2 Hardware Reset
        3. 10.3.3.3 Software Reset
      4. 10.3.4 Thermal Protection
        1. 10.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 10.3.4.2 Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Toggle Mode
      2. 10.4.2 Differential Mode
      3. 10.4.3 Power-Down Mode
    5. 10.5 Programming
      1. 10.5.1 Stand-Alone Operation
        1. 10.5.1.1 Streaming Mode Operation
      2. 10.5.2 Daisy-Chain Operation
      3. 10.5.3 Frame Error Checking
    6. 10.6 Register Maps
      1. 10.6.1  NOP Register (Offset = 00h) [reset = 0000h]
        1. Table 9. NOP Register Field Descriptions
      2. 10.6.2  DEVICEID Register (Offset = 01h) [reset = ----h]
        1. Table 10. DEVICEID Register Field Descriptions
      3. 10.6.3  STATUS Register (Offset = 02h) [reset = 0000h]
        1. Table 11. STATUS Register Field Descriptions
      4. 10.6.4  SPICONFIG Register (Offset = 03h) [reset = 0A24h]
        1. Table 12. SPICONFIG Register Field Descriptions
      5. 10.6.5  GENCONFIG Register (Offset = 04h) [reset = 7F00h]
        1. Table 13. GENCONFIG Register Field Descriptions
      6. 10.6.6  BRDCONFIG Register (Offset = 05h) [reset = FFFFh]
        1. Table 14. BRDCONFIG Register Field Descriptions
      7. 10.6.7  SYNCCONFIG Register (Offset = 06h) [reset = 0000h]
        1. Table 15. SYNCCONFIG Register Field Descriptions
      8. 10.6.8  TOGGCONFIG0 Register (Offset = 07h) [reset = 0000h]
        1. Table 16. TOGGCONFIG0 Register Field Descriptions
      9. 10.6.9  TOGGCONFIG1 Register (Offset = 08h) [reset = 0000h]
        1. Table 17. TOGGCONFIG1 Register Field Descriptions
      10. 10.6.10 DACPWDWN Register (Offset = 09h) [reset = FFFFh]
        1. Table 18. DACPWDWN Register Field Descriptions
      11. 10.6.11 DACRANGEn Register (Offset = 0Bh - 0Ch) [reset = 0000h]
        1. Table 19. DACRANGEn Register Field Descriptions
      12. 10.6.12 TRIGGER Register (Offset = 0Eh) [reset = 0000h]
        1. Table 20. TRIGGER Register Field Descriptions
      13. 10.6.13 BRDCAST Register (Offset = 0Fh) [reset = 0000h]
        1. Table 21. BRDCAST Register Field Descriptions
      14. 10.6.14 DACn Register (Offset = 14h - 1Bh) [reset = 0000h]
        1. Table 22. DACn Register Field Descriptions
      15. 10.6.15 OFFSETn Register (Offset = 21h - 22h) [reset = 0000h]
        1. Table 23. OFFSETn Register Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure for Remote Ground Tracking
        1. 11.2.2.1 Generating 300mV Offset
        2. 11.2.2.2 Amplifier Selection
        3. 11.2.2.3 Passive Component Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
    2. 14.2 関連リンク
    3. 14.3 ドキュメントの更新通知を受け取る方法
    4. 14.4 コミュニティ・リソース
    5. 14.5 商標
    6. 14.6 静電気放電に関する注意事項
    7. 14.7 Glossary
  15. 15メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

RHA Package
40-Pin VQFN
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
OUT[0:7] 5 - 8, 23 - 26 O Analog DAC output voltages.
NC 1, 2, 3, 4, 27, 28, 29, 30 O No connection.
VIO 9 PWR IO supply voltage. (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the device.
GND 10, 36 GND Ground reference point for all circuitry on the device.
SDO 11 O Serial interface data output. The SDO pin must be enabled before operation by setting the SDO-EN bit. Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by the FSDO bit (rising edge by default).
SCLK 12 I Serial interface clock.
SDI 13 I Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK pin.
CS 14 I Active low serial data enable. This input is the frame synchronization signal for the serial data. When the signal goes low, it enables the serial interface input shift register.
TOGGLE0 15 I Toggle pins. Control signals for those DAC outputs configured for toggle operation to switch between the two DAC data registers associated with each DAC. A logic low updates the DAC output to the value set by Register A. A logic high updates the DAC output to the value set by Register B. Connect the TOGGLE pins to ground if not using the toggle operation.
TOGGLE1 16 I
TOGGLE2 17 I
LDAC 18 I Active low synchronization signal. When the LDAC pin is low, the DAC outputs of those channels configured in synchronous mode are updated simultaneously. Connect to VIO if unused.
RESET 19 I Active low reset input. Logic low on this pin causes the device to issue a power-on-reset event.
CLR 20 I Active low clear input. Logic low on this pin clears all DAC outputs to their clear code. Connect to VIO if unused.
ALMOUT 21 O ALMOUT is an open drain alarm output. An external 10-kΩ pull-up resistor to a voltage no higher than VIO is required.
TEMPOUT 22 O Analog temperature monitor output.
VCC 31, 40 PWR Output positive analog power supply (9 V to 41.5 V).
VSS 32, 39 PWR Output negative analog power supply (-21.5 V to 0 V).
REF 33 I/O Reference input to the device when operating with external reference. When using internal reference, this is the reference output voltage pin. Connect a 150-nF capacitor to ground.
REFCMP 34 I/O Reference compensation capacitor connection. Connect a 330-pF capacitor between REFCMP and REFGND.
REFGND 35 GND Ground reference point for the internal reference.
VAA 37 PWR Analog supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VDD pin.
VDD 38 PWR Digital supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VAA pin.
THERMAL PAD – – The thermal pad is located on the package underside. The thermal pad should be connected to any internal PCB ground plane through multiple vias for good thermal performance.