JAJSFP9B July   2018  – June 2021 DAC61416 , DAC71416 , DAC81416

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
          1. 8.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 8.3.1.2.2 Broadcast DAC Register
          3. 8.3.1.2.3 Clear DAC Operation
      2. 8.3.2 Internal Reference
      3. 8.3.3 Device Reset Options
        1. 8.3.3.1 Power-on-Reset (POR)
        2. 8.3.3.2 Hardware Reset
        3. 8.3.3.3 Software Reset
      4. 8.3.4 Thermal Protection
        1. 8.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 8.3.4.2 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Toggle Mode
      2. 8.4.2 Differential Mode
      3. 8.4.3 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
        1. 8.5.1.1 Streaming Mode Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHA|40
サーマルパッド・メカニカル・データ
発注情報

8.5.1 Stand-Alone Operation

A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is 24 bits long with error checking disabled and 32 bits long with error checking enabled, thus the CS pin must stay low for at least 24 or 32 SCLK falling edges. The access cycle ends when the CS pin is de-asserted high. If the access cycle contains less than then minimum clock edges, the communication is ignored. If the access cycle contains more than the minimum clock edges, only the first 24 or 32 bits are used by the device. When CS is high, the SCLK and SDI signals are blocked and the SDO is in a Hi-Z state.

In an error checking disabled access cycle (24-bits long) the first byte input to SDI is the instruction cycle which identifies the request as a read or write command and the 6-bit address to be accessed. The last 16 bits in the cycle form the data cycle.

Table 8-2 Serial Interface Access Cycle
BITFIELDDESCRIPTION
23RWIdentifies the communication as a read or write command to the address register. R/W = 0 sets a write operation. R/W = 1 sets a read operation.
22xDon't care bit.
21-16A[5:0]Register address. Specifies the register to be accessed during the read or write operation.
15-0DI[15:0]Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with address A[5:0]. If a read command, the data cycle bits are don't care values.

Read operations require that the SDO pin is first enabled by setting the SDO-EN bit. A read operation is initiated by issuing a read command access cycle. After the read command, a second access cycle must be issued to get the requested data. Data are clocked out on SDO pin either on the falling edge or rising edge of SCLK according to the FSDO bit.

Table 8-3 SDO Output Access Cycle
BITFIELDDESCRIPTION
23RWEcho RW from previous access cycle.
22xEcho bit 22 from previous access cycle.
21-16A[5:0]Echo address from previous access cycle.
15-0DO[15:0]Readback data requested on previous access cycle.