JAJSFP9B July   2018  – June 2021 DAC61416 , DAC71416 , DAC81416

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
          1. 8.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 8.3.1.2.2 Broadcast DAC Register
          3. 8.3.1.2.3 Clear DAC Operation
      2. 8.3.2 Internal Reference
      3. 8.3.3 Device Reset Options
        1. 8.3.3.1 Power-on-Reset (POR)
        2. 8.3.3.2 Hardware Reset
        3. 8.3.3.3 Software Reset
      4. 8.3.4 Thermal Protection
        1. 8.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 8.3.4.2 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Toggle Mode
      2. 8.4.2 Differential Mode
      3. 8.4.3 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
        1. 8.5.1.1 Streaming Mode Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHA|40
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

Figure 6-1 RHA Package, 40-Pin VQFN, Top View
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 OUT0 Output Channel 0 analog DAC output voltage.
2 OUT1 Output Channel 1 analog DAC output voltage.
3 OUT2 Output Channel 2 analog DAC output voltage.
4 OUT3 Output Channel 3 analog DAC output voltage.
5 OUT4 Output Channel 4 analog DAC output voltage.
6 OUT5 Output Channel 5 analog DAC output voltage.
7 OUT6 Output Channel 6 analog DAC output voltage.
8 OUT7 Output Channel 7 analog DAC output voltage.
9 VIO Power IO supply voltage. (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the device.
10, 36 GND Ground Ground reference point for all circuitry on the device.
11 SDO Output Serial interface data output. The SDO pin must be enabled before operation by setting the SDO-EN bit. Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by the FSDO bit (rising edge by default).
12 SCLK Input Serial interface clock.
13 SDI Input Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK pin.
14 CS Input Active low serial data enable. This input is the frame synchronization signal for the serial data. When the signal goes low, it enables the serial interface input shift register.
15 TOGGLE0 Input Toggle pin 0. Control signal for those DAC outputs configured for toggle operation to switch between the two DAC data registers associated with each DAC. A logic low updates the DAC output to the value set by Register A. A logic high updates the DAC output to the value set by Register B. Connect the TOGGLE0 pin to ground if unused.
16 TOGGLE1 Input Toggle pin 1. Control signal for those DAC outputs configured for toggle operation to switch between the two DAC data registers associated with each DAC. A logic low updates the DAC output to the value set by Register A. A logic high updates the DAC output to the value set by Register B. Connect the TOGGLE1 pin to ground if unused.
17 TOGGLE2 Input Toggle pin 2. Control signal for those DAC outputs configured for toggle operation to switch between the two DAC data registers associated with each DAC. A logic low updates the DAC output to the value set by Register A. A logic high updates the DAC output to the value set by Register B. Connect the TOGGLE2 pin to ground if unused.
18 LDAC Input Active low synchronization signal. When the LDAC pin is low, the DAC outputs of those channels configured in synchronous mode are updated simultaneously. Connect to VIO if unused.
19 RESET Input Active low reset input. Logic low on this pin causes the device to issue a power-on-reset event.
20 CLR Input Active low clear input. Logic low on this pin clears all DAC outputs to their clear code. Connect to VIO if unused.
21 ALMOUT Output ALMOUT is an open drain alarm output. An external 10-kΩ pull-up resistor to a voltage no higher than VIO is required.
22 TEMPOUT Output Analog temperature monitor output.
23 OUT8 Output Channel 8 analog DAC output voltage.
24 OUT9 Output Channel 9 analog DAC output voltage.
25 OUT10 Output Channel 10 analog DAC output voltage.
26 OUT11 Output Channel 11 analog DAC output voltage.
27 OUT12 Output Channel 12 analog DAC output voltage.
28 OUT13 Output Channel 13 analog DAC output voltage.
29 OUT14 Output Channel 14 analog DAC output voltage.
30 OUT15 Output Channel 15 analog DAC output voltage.
31, 40 VCC Power Output positive analog power supply (9 V to 41.5 V).
32, 39 VSS Power Output negative analog power supply (–21.5 V to 0 V).
33 REF Input/Output Reference input to the device when operating with external reference. When using internal reference, this is the reference output voltage pin. Connect a 150-nF capacitor to ground.
34 REFCMP Input/Output Reference compensation capacitor connection. Connect a 330-pF capacitor between REFCMP and REFGND.
35 REFGND Ground Ground reference point for the internal reference.
37 VAA Power Analog supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VDD pin.
38 VDD Power Digital supply voltage (4.5 V to 5.5 V). This pin must be at the same potential as the VAA pin.
Thermal Pad Thermal Pad — The thermal pad is located on the package underside. Connect the thermal pad to any internal PCB ground plane through multiple vias for good thermal performance.