at TA = 25°C, VDD = 5.5 V,
external reference = 5.5 V, gain = 1 ×, 12-bit resolution, and DAC outputs unloaded
(unless otherwise noted)
| Internal reference, gain = 4 × |
Figure 6-4 Voltage Output INL vs Digital Input Code
Figure 6-6 Voltage Output INL vs Temperature
| Internal reference, gain = 4 × |
Figure 6-8 Voltage Output DNL vs Digital Input Code
Figure 6-10 Voltage Output DNL vs Temperature
| Internal reference, gain = 4 × |
Figure 6-12 Voltage Output TUE vs Digital Input Code
Figure 6-14 Voltage Output TUE vs Temperature
Figure 6-16 Voltage Output Offset Error vs Temperature
Figure 6-18 Voltage Output vs Load Current
Figure 6-20 Voltage Output Code-to-Code Glitch: Falling Edge
| Full
scale to zero scale swing |
Figure 6-22 Voltage Output Setting Time: Falling Edge
Figure 6-24 Voltage Output Power-Off Glitch
| Internal reference, gain = 4 × |
Figure 6-26 Voltage Output Noise Density
| Internal reference, gain = 4 ×, f = 0.1 Hz to 10
Hz |
Figure 6-28 Voltage Output Flicker Noise
Figure 6-30 Voltage Output AC PSRR vs Frequency
Figure 6-5 Voltage Output INL vs Digital Input Code
Figure 6-7 Voltage Output INL vs Supply Voltage
Figure 6-9 Voltage Output DNL vs Digital Input Code
Figure 6-11 Voltage Output DNL vs Supply Voltage
Figure 6-13 Voltage Output TUE vs Digital Input Code
Figure 6-15 Voltage Output TUE vs Supply Voltage
Figure 6-17 Voltage Output Gain Error vs Temperature
Figure 6-19 Voltage Output Code-to-Code Glitch - Rising Edge
| Zero
scale to full scale swing |
Figure 6-21 Voltage Output Setting Time: Rising Edge
| DAC
in Hi-Z power-down mode |
Figure 6-23 Voltage Output Power-On Glitch
| Channel 2 is resident, all other channels are
interferers |
Figure 6-25 Voltage Output Channel-to-Channel Crosstalk
Figure 6-27 Voltage Output Noise Density
Figure 6-29 Voltage Output Flicker Noise