JAJSQ26 april   2023 DAC63202W

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Digital Input/Output
      3. 7.3.3 Nonvolatile Memory (NVM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 Comparator Mode
        1. 7.4.3.1 Programmable Hysteresis Comparator
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 Fault-Dump Mode
      5. 7.4.5 Application-Specific Modes
        1. 7.4.5.1 Voltage Margining and Scaling
          1. 7.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 Function Generation
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 Device Reset and Fault Management
        1. 7.4.6.1 Power-On Reset (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 7.4.7 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
      3. 7.5.3 General-Purpose Input/Output (GPIO) Modes
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 13h, 01h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 14h, 02h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 16h, 04h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 17h, 05h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 18h, 06h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 1Ch, 19h) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      20. 7.6.20 PMBUS-PAGE Register [reset = 0300h]
      21. 7.6.21 PMBUS-OP-CMD-X Register [reset = 0000h]
      22. 7.6.22 PMBUS-CML Register [reset = 0000h]
      23. 7.6.23 PMBUS-VERSION Register [reset = 2200h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.18 Typical Characteristics: Current Output

at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)

GUID-20221114-SS0I-J9XW-K4WM-SG474GNCJKJB-low.svg
 
Figure 6-30 Current Output INL vs Digital Input Code
GUID-20221114-SS0I-GWRZ-SZMF-DXGQJRJZDGBZ-low.svg
 
Figure 6-32 Current Output INL vs Supply Voltage
GUID-20221114-SS0I-MVM9-TZ2J-2MVWLDDK9VGK-low.svg
 
Figure 6-34 Current Output DNL vs Temperature
GUID-20221114-SS0I-WSZM-6CKV-BRZC7B7VQBG3-low.svg
 
Figure 6-36 Current Output TUE vs Digital Input Code
GUID-20221114-SS0I-8LK6-ZGL2-F0LTCPZ54Q0R-low.svg
DAC channels at midscale
Figure 6-38 Current Output TUE vs Supply Voltage
GUID-20221114-SS0I-X24Z-N2SH-2JJ8RQ2BXFVS-low.svg
 
Figure 6-40 Current Output Gain Error vs Temperature
GUID-20220410-SS0I-KQFC-FW27-CNKF4C95JPBV-low.svg
 
Figure 6-42 Current Output Setting Time, Rising Edge
GUID-20220410-SS0I-9L8K-FCS9-L5VS3GBZWJK5-low.svg
DAC at mid scale (0 μA) stored in EEPROM
Figure 6-44 Current Output Power-On Glitch
GUID-20220410-SS0I-M3FP-N18V-DR5QHL2G7GDD-low.svg
 
Figure 6-46 Current Output Noise Density
GUID-20220410-SS0I-CGG4-ZLBR-4SMJR6PJLQR8-low.svg
 
Figure 6-48 Current Output AC PSRR vs Frequency
GUID-20221114-SS0I-W7T9-WJPJ-GFQJSWPSBCPV-low.svg
 
Figure 6-31 Current Output INL vs Temperature
GUID-20221114-SS0I-4H5R-WGZJ-G3CLN6RTG1VT-low.svg
 
Figure 6-33 Current Output DNL vs Digital Input Code
GUID-20221114-SS0I-GDTP-T6TW-N8DTNG2VF8F7-low.svg
 
Figure 6-35 Current Output DNL vs Supply Voltage
GUID-20221114-SS0I-1JRZ-LMKC-6GWBXTV2X2MS-low.svg
DAC channels at midscale
Figure 6-37 Current Output TUE vs Temperature
GUID-20221114-SS0I-2M5X-RLMP-WH6KPP2FTTM2-low.svg
 
Figure 6-39 Current Output Offset Error vs Temperature
GUID-20220410-SS0I-7TJZ-R75H-MNCKSS02B14P-low.svg
 
Figure 6-41 Current Output vs Load Voltage
GUID-20220410-SS0I-BDKL-KRGT-S1GNB3WWS504-low.svg
 
Figure 6-43 Current Output Setting Time, Falling Edge
GUID-20220410-SS0I-VZ75-JXTT-LSS9PBSHH8HB-low.svg
DAC at mid scale (0 μA)
Figure 6-45 Current Output Power-Off Glitch
GUID-20220410-SS0I-WFHV-Q84G-3X31F69MSKCK-low.svg
f = 0.1 Hz to 10 Hz
Figure 6-47 Current Output Flicker Noise