JAJSLO3A March 2021 – December 2021
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE | ||||||
Resolution | DAC63204 | 12 | Bits | |||
DAC53204 | 10 | |||||
DAC43204 | 8 | |||||
INL | Integral nonlinearity(1) | DAC63204 | –4 | 4 | LSB | |
DAC53204, DAC43204 | –1 | 1 | ||||
DNL | Differential nonlinearity(1) | –1 | 1 | LSB | ||
Zero-code error(4) | Code 0d into DAC, external reference, VDD = 5.5 V | 6 | 12 | mV | ||
Code 0d into DAC, internal VREF, gain = 4x, VDD = 5.5 V |
6 | 15 | ||||
Zero-code error temperature coefficient(4) | Code 0d into DAC | ±10 | µV/°C | |||
Offset error(4) (6) | 1.7 V ≤ VDD < 2.7 V, FBx pin shorted to OUTx, DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution, 2d for 8-bit resolution | –0.75 | 0.3 | 0.75 | %FSR | |
2.7 V ≤ VDD ≤ 5.5 V, FBx pin shorted to OUTx, DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution, 2d for 8-bit resolution | –0.5 | 0.25 | 0.5 | |||
Offset-error temperature coefficient(4) | FBx pin shorted to OUTx, DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution, 2d for 8-bit resolution |
±0.0003 | %FSR/°C | |||
Gain error(4) | Between end-point codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution | –0.5 | 0.25 | 0.5 | %FSR | |
Gain-error temperature coefficient(4) | Between end-point codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution | ±0.0008 | %FSR/°C | |||
Full-scale error(4) (6) | 1.7 V ≤ VDD < 2.7 V, DAC at full-scale | –1 | 1 | %FSR | ||
2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale | –0.5 | 0.5 | ||||
Full-scale-error temperature coefficient(4) | DAC at full-scale | ±0.0008 | %FSR/°C | |||
OUTPUT | ||||||
Output voltage | Reference tied to VDD | 0 | VDD | V | ||
CL | Capacitive load(2) | RL = infinite, phase margin = 30° | 200 | pF | ||
Phase margin = 30° | 1000 | |||||
Short-circuit current | VDD = 1.7 V, full-scale output shorted to AGND or zero-scale output shorted to VDD |
15 | mA | |||
VDD = 2.7 V, full-scale output shorted to AGND or zero-scale output shorted to VDD |
50 | |||||
VDD = 5.5 V, full-scale output shorted to AGND or zero-scale output shorted to VDD |
60 | |||||
Output-voltage headroom(2) | To VDD (DAC output unloaded, internal reference = 1.21 V), VDD ≥ 1.21 V ☓ gain + 0.2 V | 0.2 | V | |||
To VDD and AGND (DAC output unloaded, external reference at VDD, gain = 1x, the VREF pin is not shorted to VDD) | 0.8 | %FSR | ||||
To VDD and AGND (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), external reference at VDD, gain = 1x, the VREF pin is not shorted to VDD | 10 | |||||
ZO | VFB dc output impedance(3) | DAC output enabled, internal reference (gain = 1.5x or 2x) or external reference at VDD (gain = 1x), the VREF pin is not shorted to VDD | 400 | 500 | 600 | kΩ |
DAC output enabled, internal VREF, gain = 3x or 4x | 325 | 400 | 485 | |||
Power supply rejection ratio (dc) | Internal VREF, gain = 2x, DAC at midscale, VDD = 5 V ±10% |
0.25 | mV/V | |||
DYNAMIC PERFORMANCE | ||||||
tsett | Output voltage settling time | 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V | 20 | µs | ||
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4x | 25 | |||||
Slew rate | VDD = 5.5 V | 0.3 | V/µs | |||
Power-on glitch magnitude | At startup (DAC output disabled) | 75 | mV | |||
At startup (DAC output disabled), RL = 100 kΩ | 200 | |||||
Output-enable glitch magnitude | DAC output disabled to enabled (DAC registers at zero scale), RL = 100 kΩ | 250 | mV | |||
Vn | Output noise voltage (peak to peak) | f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V | 50 | µVPP | ||
Internal VREF, gain = 4x, f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V |
90 | |||||
Output noise density | f = 1 kHz, DAC at midscale, VDD = 5.5 V | 0.35 | µV/√Hz | |||
Internal VREF, gain = 4x, f = 1 kHz, DAC at midscale, VDD = 5.5 V | 0.9 | |||||
Power supply rejection ratio (ac)(3) | Internal VREF, gain = 4x, 200-mV 50-Hz or 60-Hz sine wave superimposed on power supply voltage, DAC at midscale | -68 | dB | |||
Code change glitch impulse | ±1 LSB change around midscale (including feedthrough) | 10 | nV-s | |||
Code change glitch impulse magnitude | ±1 LSB change around midscale (including feedthrough) | 15 | mV | |||
POWER | ||||||
IDD | Current flowing into VDD(4) (5) | Normal operation, DACs at full scale, digital pins static, external reference at VDD but the VREF pin is not shorted to VDD | 150 | µA/ch |