JAJSFQ0A July 2018 – November 2018 DAC61408 , DAC71408 , DAC81408
PRODUCTION DATA.
The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register and DAC output on a CS rising edge. In synchronous mode, writing to the DAC data register doe not automatically update the DAC output. Instead the update occurs only after a trigger event. A DAC trigger signal is generated either through the LDAC bit or by the LDAC pin. The synchronous update mode enables simultaneous update of multiple DAC outputs. In both update modes a minimum wait time of 1 µs is required between DAC output updates.