JAJSEY9E April 2005 – March 2018 DAC7811
PRODUCTION DATA.
The input shift register is 16 bits wide, as shown in Figure 1. The four MSBs are the control bits C3–C0; these bits determine which function will be executed at the rising edge of SYNC in daisy-chain mode or the 16th active clock edge in stand-alone mode. The remaining 12 bits are the data bits. On a load and update command (C3–C0 = 0001) these 12 data bits will be transferred to the DAC register; otherwise, they have no effect. Table 2 shows serial shift register and DAC register operation with CLK and SYNC pin settings.
4 CONTROL BITS | 12 DATA BITS | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
B15 (MSB) | B14 | B13 | B12 | B11 | B10 | B9 | B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 (LSB) |
C3 | C2 | C1 | C0 | DB11 | DB0 |
CLK | SYNC | SERIAL SHIFT REGISTER | DAC REGISTER |
---|---|---|---|
X | H | No effect | Latched |
↓– | L | Shift register data advanced one bit | Latched |
X | ↑+ | In daisy-chain mode, the function as determined by C3-C0 is executed. | In daisy-chain mode, the contents may change as determined by C3-C0. |