JAJSI90A November   2019  – April 2020 DAC60502 , DAC70502 , DAC80502

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Requirements : SPI Mode
    7. 8.7  Timing Requirements : I2C Standard Mode
    8. 8.8  Timing Requirements : I2C Fast Mode
    9. 8.9  Timing Requirements : I2C Fast-Mode Plus
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 9.3.1.1 DAC Transfer Function
        2. 9.3.1.2 DAC Register Structure
        3. 9.3.1.3 Output Amplifier
      2. 9.3.2 Internal Reference
        1. 9.3.2.1 Solder Heat Reflow
      3. 9.3.3 Power-On Reset (POR)
      4. 9.3.4 Software Reset
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 SPI Mode
          1. 9.5.1.1.1 SYNC Interrupt
        2. 9.5.1.2 I2C Mode
          1. 9.5.1.2.1 F/S Mode Protocol
          2. 9.5.1.2.2 DACx0502 I2C Update Sequence
            1. 9.5.1.2.2.1 DACx0502 Address Byte
            2. 9.5.1.2.2.2 DACx0502 Command Byte
            3. 9.5.1.2.2.3 DACx0502 Data Byte (MSDB and LSDB)
          3. 9.5.1.2.3 DACx0502 I2C Read Sequence
    6. 9.6 Register Maps
      1. 9.6.1 Registers
        1. 9.6.1.1 NOOP Register (offset = 0h) [reset = 0000h]
          1. Table 9. NOOP Register Field Descriptions
        2. 9.6.1.2 DEVID Register (offset = 1h) [reset = 0214h for DAC80502, 1214h for DAC70502, 2214h for DAC60502]
          1. Table 10. DEVID Register Field Descriptions
        3. 9.6.1.3 SYNC Register (offset = 2h) [reset = 0300h]
          1. Table 11. SYNC Register Field Descriptions
        4. 9.6.1.4 CONFIG Register (offset = 3h) [reset = 0000h]
          1. Table 12. CONFIG Register Field Descriptions
        5. 9.6.1.5 GAIN Register (offset = 4h) [reset = 0003h]
          1. Table 13. GAIN Register Field Descriptions
        6. 9.6.1.6 TRIGGER Register (offset = 5h) [reset = 0000h]
          1. Table 14. TRIGGER Register Field Descriptions
        7. 9.6.1.7 BRDCAST Register (offset = 6h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
          1. Table 15. BRDCAST Register Field Descriptions
        8. 9.6.1.8 STATUS Register (offset = 7h) [reset = 0000h]
          1. Table 16. STATUS Register Field Descriptions
        9. 9.6.1.9 DAC-n Register (offset = 8h–9h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
          1. Table 17. DAC-A Data Register Field Descriptions (8h)
          2. Table 18. DAC-B Data Register Field Descriptions (9h)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 SPI Connection to a Processor
      2. 10.3.2 I2C Interface Connection to a Processor
    4. 10.4 What To Do and What Not To Do
      1. 10.4.1 What To Do
      2. 10.4.2 What Not To Do
    5. 10.5 Initialization Setup
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.5.1.2.2 DACx0502 I2C Update Sequence

For a single update, the DACx0502 requires a start condition, a valid I2C address byte, a command byte, and two data bytes (the most significant data byte, MSDB, and least significant data byte, LSDB), as listed in Table 2.

Table 2. Update Sequence

MSB .... LSB ACK MSB ... LSB ACK MSB ... LSB ACK MSB ... LSB ACK
Address (A) byte Command byte MSDB LSDB
DB [31:24] DB [23:16] DB [15:8] DB [7:0]

After each byte is received, the DACx0502 acknowledges the byte by pulling the SDA line low during the high period of a single clock pulse, as shown in Figure 62. These four bytes and acknowledge cycles make up the 36 clock cycles required for a single update to occur. A valid I2C™ address byte selects the DACx0502 devices.

DAC80502 DAC70502 DAC60502 SBAS793_DACx0502_I2C_Bus_Protocol.gifFigure 62. I2C Bus Protocol

The command byte sets the operating mode of the selected DACx0502 device. When the operating mode is selected by this byte, the DACx0502 series must receive two data bytes, the most significant data byte (MSDB) and least significant data byte (LSDB), for a data update to occur. The DACx0502 devices perform an update on the falling edge of the acknowledge signal that follows the LSDB.

When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 22.22 kSPS. Using the fast-mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 55.55 kSPS. When a stop condition is received, the DACx0502 family releases the I2C bus and awaits a new start condition.