JAJSFP9B July   2018  – June 2021 DAC61416 , DAC71416 , DAC81416

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
          1. 8.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 8.3.1.2.2 Broadcast DAC Register
          3. 8.3.1.2.3 Clear DAC Operation
      2. 8.3.2 Internal Reference
      3. 8.3.3 Device Reset Options
        1. 8.3.3.1 Power-on-Reset (POR)
        2. 8.3.3.2 Hardware Reset
        3. 8.3.3.3 Software Reset
      4. 8.3.4 Thermal Protection
        1. 8.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 8.3.4.2 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Toggle Mode
      2. 8.4.2 Differential Mode
      3. 8.4.3 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
        1. 8.5.1.1 Streaming Mode Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHA|40
サーマルパッド・メカニカル・データ
発注情報
8.3.1.2.1 DAC Register Synchronous and Asynchronous Updates

The update mode for each DAC channel is determined by the status of its corresponding SYNC-EN bit. In asynchronous mode, a write to the DAC data register results in an immediate update of the DAC active register and DAC output on a CS rising edge. In synchronous mode, writing to the DAC data register does not automatically update the DAC output. Instead the update occurs only after a trigger event. A DAC trigger signal is generated either through the LDAC bit or by the LDAC pin. The synchronous update mode enables simultaneous update of multiple DAC outputs. In both update modes a minimum wait time of 1 µs is required between DAC output updates.