JAJSFP9B July   2018  – June 2021 DAC61416 , DAC71416 , DAC81416

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
          1. 8.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 8.3.1.2.2 Broadcast DAC Register
          3. 8.3.1.2.3 Clear DAC Operation
      2. 8.3.2 Internal Reference
      3. 8.3.3 Device Reset Options
        1. 8.3.3.1 Power-on-Reset (POR)
        2. 8.3.3.2 Hardware Reset
        3. 8.3.3.3 Software Reset
      4. 8.3.4 Thermal Protection
        1. 8.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 8.3.4.2 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Toggle Mode
      2. 8.4.2 Differential Mode
      3. 8.4.3 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
        1. 8.5.1.1 Streaming Mode Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHA|40
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

all minimum/maximum specifications at TA = –40℃ to +125℃ and all typical specifications at TA = 25℃, VCC = 9 V to 41.5 V, VSS = –21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, digital inputs at VIO or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution DAC81416 16 Bits
DAC71416 14
DAC61416 12
INL Integral nonlinearity DAC81416, all ranges, except 0 V to 40 V and ±2.5 V –1 ±0.5 1 LSB
DAC81416, 0 V to 40 V and ±2.5-V ranges –2 ±1 2
DAC71416, all ranges –1 ±0.5 1
DAC61416, all ranges –1 ±0.5 1
DNL Differential nonlinearity DAC81416, specified 16-bit monotonic –1 ±0.5 1 LSB
DAC71416, specified 14-bit monotonic –1 ±0.5 1
DAC61416, specified 12-bit monotonic –1 ±0.5 1
TUE Total unadjusted error All ranges, except ±2.5 V –0.1 ±0.01 0.1 %FSR
±2.5-V range –0.2 ±0.02 0.2
Unipolar offset error All unipolar ranges –0.03 ±0.015 0.03 %FSR
Unipolar zero-code error All unipolar ranges 0 0.04 0.1 %FSR
Bipolar zero error All bipolar ranges –0.2 ±0.02 0.2 %FSR
Full-scale error All ranges –0.2 ±0.075 0.2 %FSR
Gain error All ranges, except ±2.5 V –0.1 ±0.02 0.1 %FSR
±2.5-V range –0.2 ±0.02 0.2
Unipolar offset error drift All unipolar ranges ±2 ppm of FSR/°C
Bipolar zero error drift All bipolar ranges ±2 ppm of FSR/°C
Gain error drift All ranges ±2 ppm of FSR/°C
Output voltage drift over time TA = 40°C, full-scale code, 1900 hours 5 ppm of FSR
DIFFERENTIAL MODE PERFORMANCE(1)
TUE Total unadjusted error All ranges –0.1 ±0.01 0.1 %FSR
±2.5-V range –0.2 ±0.02 0.2
Common-mode error All bipolar ranges, midscale code –0.1 ±0.01 0.1 %FSR
OUTPUT CHARACTERISTICS
Output voltage headroom To VSS and VCC
(–10 mA ≤ IOUT ≤ 10 mA) 		 1 V
To VSS and VCC
(–15 mA ≤ IOUT ≤ 15 mA)		 1.5
Short-circuit current(2) Full-scale output shorted to VSS 40 mA
Zero-scale output shorted to VCC 40
Load regulation Midscale code, –15 mA ≤ IOUT ≤ 15 mA 70 μV/mA
Maximum capacitive load(3) RLOAD = open 0 1 nF
DC output impedance Midscale code 0.05 Ω
Full-scale code 40
DYNAMIC PERFORMANCE
Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling time to ±1 LSB, ±10-V range,
RL = 5 kΩ, CL = 200 pF		 12 µs
Slew rate 0-V to 5-V range 1 V/µs
All other output ranges 4
Power-on glitch magnitude Power-down to active DAC output,
±20 V range, midscale code,
RL = 5 kΩ, CL = 200 pF		 0.3 V
Output noise 0.1 Hz to 10 Hz, midscale code,
0-V to 5-V range		 15 µVpp
Output noise density 1 kHz, midscale code, 0-V to 5-V range 78 nV/Hz
PSRR-AC Power supply ac rejection ratio Midscale code, frequency = 60 Hz, amplitude = 200 mVpp superimposed on VDD, VCC or VSS 1 LSB/V
PSRR-DC Power supply dc rejection ratio Midscale code, VDD = 5 V ± 5%,
VCC = 20 V, VSS = –20 V		 1 LSB/V
Midscale code, VDD = 5 V,
VCC = 20 V ± 5%, VSS = –20 V		 1
Midscale code, VDD = 5 V,
VCC = 20 V, VSS = –20 V ± 5%		 1
Code change glitch impulse 1-LSB change around major carrier,
0-V to 5-V range		 4 nV-s
Channel-to-channel ac crosstalk 0-V to 5-V range, measured channel at midscale, full-scale swing on all other channels 4 nV-s
Channel-to-channel dc crosstalk 0-V to 5-V range, measured channel at midscale, all other channels at full-scale 0.25 LSB
Digital feedthrough 0-V to 5-V range, midscale code,
fSCLK = 1 MHz		 1 nV-s
EXTERNAL REFERENCE INPUT
VREFIN Reference input voltage range To VREFGND 2.49 2.5 2.51 V
Reference input current 50 µA
Reference input impedance 50 kΩ
Reference input capacitance 20 pF
INTERNAL REFERENCE
VREFOUT Reference output voltage range TA = 25°C 2.4975 2.5025 V
Reference output drift 5 15 ppm/°C
Reference output impedance 0.1 Ω
Reference output noise 0.1 Hz to 10 Hz 12 µVpp
Reference output noise density 10 kHz, REFLOAD = 10 nF 150 nV/Hz
Reference load current 5 mA
Reference load regulation Source 80 µV/mA
Reference line regulation 20 µV/V
Reference output drift over time TA = 25°C, 1900 hours 250 µV
Reference thermal hysteresis First cycle ±700 µV
Additional cycle ±50
DIGITAL INPUTS AND OUTPUTS
VIH High-level input voltage 0.7 × VIO V
VIL Low-level input voltage 0.3 × VIO V
Input current ±2 µA
Input pin capacitance 2 pF
VOH High-level output voltage IOH = 0.2 mA VIO – 0.2 V
VOL Low-level output voltage IOL = 0.2 mA 0.4 V
Output pin capacitance 5 pF
ALARM OUTPUT
Output pin capacitance 5 pF
VOL Low-level output voltage ILOAD = –0.2 mA 0.4 V
TEMPERATURE OUTPUT
VTEMPOUT,0C Output voltage offset at 0℃ 1.34 V
Sensor gain –4 mV/°C
POWER REQUIREMENTS
IDD VDD supply current Active mode, internal reference enabled, full-scale code, ±20 V output range, SPI static 0.05 0.5 mA
Active mode, internal reference disabled, full-scale code, ±20 V output range, SPI static 0.05 0.5 mA
Power-down mode 0.05 0.5 mA
IAA VAA supply current Active mode, internal reference enabled, full-scale code, ±20 V output range, SPI static 20 30 mA
Active mode, internal reference disabled, full-scale code, ±20 V output range, SPI static 18 28 mA
Power-down mode 2 85 µA
ICC VCC supply current Active mode, internal reference enabled, full-scale code, ±20 V output range, SPI static 10 25 mA
Active mode, internal reference disabled, full-scale code, ±20 V output range, SPI static 10 25 mA
Power-down mode 10 30 µA
 ISS VSS supply current Active mode, internal reference enabled, full-scale code, ±20 V output range, SPI static –15 –10 mA
Active mode, internal reference disabled, full-scale code, ±20 V output range, SPI static –15 –10 mA
Power-down mode –30 –10 µA
IIO VIO supply current SCLK and SDI toggling at 50 MHz 350 500 µA
(1) End point fit between codes. 16-bit: Code 256 to 65280, 14-bit: Code 128 to 16256, 12-bit: Code 32 to 4064.
(2) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified maximum junction temperature may impair device reliability.
(3) Specified by design and characterization, not production tested.