SLAS719E August 2010 – June 2015 DAC7562 , DAC7563 , DAC8162 , DAC8163 , DAC8562 , DAC8563
PRODUCTION DATA.
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE(1) | ||||||
DAC856x | Resolution | 16 | Bits | |||
Relative accuracy | Using line passing through codes 512 and 65,024 | ±4 | ±12 | LSB | ||
Differential nonlinearity | 16-bit monotonic | ±0.2 | ±1 | LSB | ||
DAC816x | Resolution | 14 | Bits | |||
Relative accuracy | Using line passing through codes 128 and 16,256 | ±1 | ±3 | LSB | ||
Differential nonlinearity | 14-bit monotonic | ±0.1 | ±0.5 | LSB | ||
DAC756x | Resolution | 12 | Bits | |||
Relative accuracy | Using line passing through codes 32 and 4,064 | ±0.3 | ±0.75 | LSB | ||
Differential nonlinearity | 12-bit monotonic | ±0.05 | ±0.25 | LSB | ||
Offset error | Extrapolated from two-point line(1), unloaded | ±1 | ±4 | mV | ||
Offset error drift | ±2 | µV/°C | ||||
Full-scale error | DAC register loaded with all 1s | ±0.03 | ±0.2 | % FSR | ||
Zero-code error | DAC register loaded with all 0s | 1 | 4 | mV | ||
Zero-code error drift | ±2 | µV/°C | ||||
Gain error | Extrapolated from two-point line(1), unloaded | ±0.01 | ±0.15 | % FSR | ||
Gain temperature coefficient | ±1 | ppm FSR/°C | ||||
OUTPUT CHARACTERISTICS(2) | ||||||
Output voltage range | 0 | AVDD | V | |||
Output voltage settling time(3) | DACs unloaded | 7 | µs | |||
RL = 1 MΩ | 10 | |||||
Slew rate | Measured between 20%–80% of a full-scale transition | 0.75 | V/µs | |||
Capacitive load stability | RL = ∞ | 1 | nF | |||
RL = 2 kΩ | 3 | |||||
Code-change glitch impulse | 1-LSB change around major carry | 0.1 | nV-s | |||
Digital feedthrough | SCLK toggling, SYNC high | 0.1 | nV-s | |||
Power-on glitch impulse | RL = 2 kΩ, CL = 470 pF, AVDD = 5.5 V | 40 | mV | |||
Channel-to-channel dc crosstalk | Full-scale swing on adjacent channel, External reference |
5 | µV | |||
Full-scale swing on adjacent channel, Internal reference |
15 | |||||
DC output impedance | At mid-scale input | 5 | Ω | |||
Short-circuit current | DAC outputs at full-scale, DAC outputs shorted to GND | 40 | mA | |||
Power-up time, including settling time | Coming out of power-down mode | 50 | µs | |||
AC PERFORMANCE(2) | ||||||
DAC output noise density | TA = 25°C, at mid-scale input, fOUT = 1 kHz | 90 | nV/√Hz | |||
DAC output noise | TA = 25°C, at mid-scale input, 0.1 Hz to 10 Hz | 2.6 | µVPP | |||
LOGIC INPUTS(2) | ||||||
Input-pin leakage current | –1 | ±0.1 | 1 | µA | ||
Logic input LOW voltage VIL | 0 | 0.8 | V | |||
Logic input HIGH voltage VIH | 0.7 × AVDD | AVDD | V | |||
Pin capacitance | 3 | pF | ||||
REFERENCE | ||||||
External reference current | External VREF = 2.5 V (when internal reference is disabled), all channels active using gain = 1 | 15 | µA | |||
Reference input impedance | Internal reference disabled, gain = 1 | 170 | kΩ | |||
Internal reference disabled, gain = 2 | 85 | |||||
REFERENCE OUTPUT | ||||||
Output voltage | TA = 25°C | 2.495 | 2.5 | 2.505 | V | |
Initial accuracy | TA = 25°C | –5 | ±0.1 | 5 | mV | |
Output-voltage temperature drift | 4 | 10 | ppm/°C | |||
Output-voltage noise | f = 0.1 Hz to 10 Hz | 12 | µVPP | |||
Output-voltage noise density (high-frequency noise) | TA = 25°C, f = 1 kHz, CL = 0 µF | 250 | nV/√Hz | |||
TA = 25°C, f = 1 MHz, CL = 0 µF | 30 | |||||
TA = 25°C, f = 1 MHz, CL = 4.7 µF | 10 | |||||
Load regulation, sourcing(4) | TA = 25°C | 20 | µV/mA | |||
Load regulation, sinking(4) | TA = 25°C | 185 | µV/mA | |||
Output-current load capability(2) | ±20 | mA | ||||
Line regulation | TA = 25°C | 50 | µV/V | |||
Long-term stability or drift (aging)(4) | TA = 25°C, time = 0 to 1900 hours | 100 | ppm | |||
Thermal hysteresis(4) | First cycle | 200 | ppm | |||
Additional cycles | 50 | |||||
POWER REQUIREMENTS(5) | ||||||
Power supply current (IDD) | AVDD = 3.6 V to 5.5 V, normal mode, internal reference off | 0.25 | 0.5 | mA | ||
AVDD = 3.6 V to 5.5 V, normal mode, internal reference on | 0.9 | 1.6 | ||||
AVDD = 3.6 V to 5.5 V, power-down modes(6) | 0.55 | 2 | µA | |||
AVDD = 3.6 V to 5.5 V, power-down modes | 0.55 | 4 | ||||
AVDD = 2.7 V to 3.6 V, normal mode, internal reference off | 0.2 | 0.4 | mA | |||
AVDD = 2.7 V to 3.6 V, normal mode, internal reference on | 0.73 | 1.4 | ||||
AVDD = 2.7 V to 3.6 V, power-down modes(6) | 0.35 | 2 | µA | |||
AVDD = 2.7 V to 3.6 V, power-down modes | 0.35 | 3 | ||||
Power dissipation | AVDD = 3.6 V to 5.5 V, normal mode, internal reference off | 0.9 | 2.75 | mW | ||
AVDD = 3.6 V to 5.5 V, normal mode, internal reference on | 3.2 | 8.8 | ||||
AVDD = 3.6 V to 5.5 V, power-down modes(6) | 2 | 11 | µW | |||
AVDD = 3.6 V to 5.5 V, power-down modes | 2 | 22 | ||||
AVDD = 2.7 V to 3.6 V, normal mode, internal reference off | 0.54 | 1.44 | mW | |||
AVDD = 2.7 V to 3.6 V, normal mode, internal reference on | 1.97 | 5 | ||||
AVDD = 2.7 V to 3.6 V, power-down modes(6) | 0.95 | 7.2 | µW | |||
AVDD = 2.7 V to 3.6 V, power-down modes | 0.95 | 10.8 |
MEASUREMENT | POWER-SUPPLY VOLTAGE | FIGURE NUMBER | |
---|---|---|---|
Internal Reference Voltage vs Temperature | 5.5 V | Figure 2 | |
Internal Reference Voltage Temperature Drift Histogram | Figure 3 | ||
Internal Reference Voltage vs Load Current | Figure 4 | ||
Internal Reference Voltage vs Time | Figure 5 | ||
Internal Reference Noise Density vs Frequency | Figure 6 | ||
Internal Reference Voltage vs Supply Voltage | 2.7 V–5.5 V | Figure 7 |
MEASUREMENT | POWER-SUPPLY VOLTAGE | FIGURE NUMBER | |
---|---|---|---|
FULL-SCALE, GAIN, OFFSET AND ZERO-CODE ERRORS | |||
Full-Scale Error vs Temperature | 5.5 V | Figure 16 | |
Gain Error vs Temperature | Figure 17 | ||
Offset Error vs Temperature | Figure 18 | ||
Zero-Code Error vs Temperature | Figure 19 | ||
Full-Scale Error vs Temperature | 2.7 V | Figure 63 | |
Gain Error vs Temperature | Figure 64 | ||
Offset Error vs Temperature | Figure 65 | ||
Zero-Code Error vs Temperature | Figure 66 | ||
LOAD REGULATION | |||
DAC Output Voltage vs Load Current | 5.5 V | Figure 30 | |
2.7 V | Figure 74 | ||
DIFFERENTIAL NONLINEARITY ERROR | |||
Differential Linearity Error vs Digital Input Code | T = –40°C | 5.5 V | Figure 9 |
T = 25°C | Figure 11 | ||
T = 125°C | Figure 13 | ||
Differential Linearity Error vs Temperature | Figure 15 | ||
Differential Linearity Error vs Digital Input Code | T = –40°C | 2.7 V | Figure 56 |
T = 25°C | Figure 58 | ||
T = 125°C | Figure 60 | ||
Differential Linearity Error vs Temperature | Figure 62 | ||
INTEGRAL NONLINEARITY ERROR (RELATIVE ACCURACY) | |||
Linearity Error vs Digital Input Code | T = –40°C | 5.5 V | Figure 8 |
T = 25°C | Figure 10 | ||
T = 125°C | Figure 12 | ||
Linearity Error vs Temperature | Figure 14 | ||
Linearity Error vs Digital Input Code | T = –40°C | 2.7 V | Figure 55 |
T = 25°C | Figure 57 | ||
T = 125°C | Figure 59 | ||
Linearity Error vs Temperature | Figure 61 | ||
POWER-DOWN CURRENT | |||
Power-Down Current vs Temperature | 5.5 V | Figure 28 | |
Power-Down Current vs Power-Supply Voltage | 2.7 V – 5.5 V | Figure 29 | |
Power-Down Current vs Temperature | 2.7 V | Figure 73 | |
POWER-SUPPLY CURRENT | |||
Power-Supply Current vs Temperature | External VREF | 5.5 V | Figure 20 |
Internal VREF | Figure 21 | ||
Power-Supply Current vs Digital Input Code | External VREF | Figure 22 | |
Internal VREF | Figure 23 | ||
Power-Supply Current Histogram | External VREF | Figure 24 | |
Internal VREF | Figure 25 | ||
Power-Supply Current vs Power-Supply Voltage | External VREF | 2.7 V – 5.5 V | Figure 26 |
Internal VREF | Figure 27 | ||
Power-Supply Current vs Temperature | External VREF | 3.6 V | Figure 49 |
Internal VREF | Figure 50 | ||
Power-Supply Current vs Digital Input Code | External VREF | Figure 51 | |
Internal VREF | Figure 52 | ||
Power-Supply Current Histogram | External VREF | Figure 53 | |
Internal VREF | Figure 54 | ||
Power-Supply Current vs Temperature | External VREF | 2.7 V | Figure 67 |
Internal VREF | Figure 68 | ||
Power-Supply Current vs Digital Input Code | External VREF | Figure 69 | |
Internal VREF | Figure 70 | ||
Power-Supply Current Histogram | External VREF | Figure 71 | |
Internal VREF | Figure 72 |
MEASUREMENT | POWER-SUPPLY VOLTAGE | FIGURE NUMBER | |
---|---|---|---|
CHANNEL-TO-CHANNEL CROSSTALK | |||
Channel-to-Channel Crosstalk | 5-V Rising Edge | 5.5 V | Figure 43 |
5-V Falling Edge | Figure 44 | ||
CLOCK FEEDTHROUGH | |||
Clock Feedthrough | 500 kHz, Midscale | 5.5 V | Figure 48 |
2.7 V | Figure 87 | ||
GLITCH IMPULSE | |||
Glitch Impulse, 1-LSB Step | Rising Edge, Code 7FFFh to 8000h | 5.5 V | Figure 37 |
Falling Edge, Code 8000h to 7FFFh | Figure 38 | ||
Glitch Impulse, 4-LSB Step | Rising Edge, Code 7FFCh to 8000h | Figure 39 | |
Falling Edge, Code 8000h to 7FFCh | Figure 40 | ||
Glitch Impulse, 16-LSB Step | Rising Edge, Code 7FF0h to 8000h | Figure 41 | |
Falling Edge, Code 8000h to 7FF0h | Figure 42 | ||
Glitch Impulse, 1-LSB Step | Rising Edge, Code 7FFFh to 8000h | 2.7 V | Figure 79 |
Falling Edge, Code 8000h to 7FFFh | Figure 80 | ||
Glitch Impulse, 4-LSB Step | Rising Edge, Code 7FFCh to 8000h | Figure 81 | |
Falling Edge, Code 8000h to 7FFCh | Figure 82 | ||
Glitch Impulse, 16-LSB Step | Rising Edge, Code 7FF0h to 8000h | Figure 83 | |
Falling Edge, Code 8000h to 7FF0h | Figure 84 | ||
NOISE | |||
DAC Output Noise Density vs Frequency | External VREF | 5.5 V | Figure 45 |
Internal VREF | Figure 46 | ||
DAC Output Noise 0.1 Hz to 10 Hz | External VREF | Figure 47 | |
POWER-ON GLITCH | |||
Power-On Glitch | Reset to Zero Scale | 5.5 V | Figure 35 |
Reset to Midscale | Figure 36 | ||
Reset to Zero Scale | 2.7 V | Figure 85 | |
Reset to Midscale | Figure 86 | ||
SETTLING TIME | |||
Full-Scale Settling Time | Rising Edge, Code 0h to FFFFh | 5.5 V | Figure 31 |
Falling Edge, Code FFFFh to 0h | Figure 32 | ||
Half-Scale Settling Time | Rising Edge, Code 4000h to C000h | Figure 33 | |
Falling Edge, Code C000h to 4000h | Figure 34 | ||
Full-Scale Settling Time | Rising Edge, Code 0h to FFFFh | 2.7 V | Figure 75 |
Falling Edge, Code FFFFh to 0h | Figure 76 | ||
Half-Scale Settling Time | Rising Edge, Code 4000h to C000h | Figure 77 | |
Falling Edge, Code C000h to 4000h | Figure 78 |