JAJSGM3 December   2018 DAC8742H

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  HART Modulator
      2. 7.3.2  HART Demodulator
      3. 7.3.3  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Encoder
      4. 7.3.4  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Decoder
      5. 7.3.5  Internal Reference
      6. 7.3.6  Clock Configuration
      7. 7.3.7  Reset and Power-Down
      8. 7.3.8  Full-Duplex Mode
      9. 7.3.9  I/O Selection
      10. 7.3.10 Jabber Inhibitor
    4. 7.4 Device Functional Modes
      1. 7.4.1 UART Interfaced HART
      2. 7.4.2 UART Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
      3. 7.4.3 SPI Interfaced HART
      4. 7.4.4 SPI Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
      5. 7.4.5 Interface
        1. 7.4.5.1 UART
          1. 7.4.5.1.1 UART Carrier Detect
        2. 7.4.5.2 SPI
          1. 7.4.5.2.1 SPI Cyclic Redundancy Check
          2. 7.4.5.2.2 SPI Interrupt Request
    5. 7.5 Register Maps
      1. 7.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 4. CONTROL Register Field Descriptions
      2. 7.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 5. RESET Register Field Descriptions
      3. 7.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 6. MODEM_STATUS Register Field Descriptions
      4. 7.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 7. MODEM_IRQ_MASK Register Field Descriptions
      5. 7.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 8. MODEM_CONTROL Register Field Descriptions
      6. 7.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 9. FIFO_D2M Register Field Descriptions
      7. 7.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 10. FIFO_M2D Register Field Descriptions
      8. 7.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 11. FIFO_LEVEL_SET Register Field Descriptions
      9. 7.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 12. PAFF_JABBER Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Design Recommendations
      2. 8.1.2 Selecting the Crystal/Resonator
      3. 8.1.3 Included Functions and Filter Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DAC8742H HART Modem
        2. 8.2.2.2 2-Wire Current Loop
        3. 8.2.2.3 Regulator
        4. 8.2.2.4 DAC
        5. 8.2.2.5 Amplifiers
        6. 8.2.2.6 Diodes
        7. 8.2.2.7 Passives
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Typical Characteristics

DAC8742H D002_SBAS856_HART_EXT_BPF.gif
Figure 2. HART Mode External Band-Pass Filter Response
DAC8742H D004_SBAS856_PAFF_EXT_BPF.gif
Figure 4. FF / PA Mode External Band-Pass Filter Response
DAC8742H D006_SBAS856_VREF_v_AVDD.gif
Figure 6. Internal Reference Voltage versus AVDD
DAC8742H D008_SBAS856_HART_Carrier_Start.gif
Figure 8. HART TX Carrier Start Time
DAC8742H D010_SBAS856_HART_RX_Stop.gif
Figure 10. HART RX Carrier Detect Off Timing
DAC8742H D012_SBAS856_IOVDD_Current_EXT_REF.gif
Figure 12. HART Mode IOVDD Supply Current versus Voltage with External Reference
DAC8742H D016_SBAS856_IOVDD_Current_INT_REF.gif
Figure 14. HART Mode IOVDD Supply Current versus Voltage with Internal Reference
DAC8742H D014_SBAS856_PAFF_IOVDD_IQ_EXT_REF.gif
Figure 16. FF / PA Mode IOVDD Supply Current versus Voltage with External Reference
DAC8742H D018_SBAS856_PAFF_IOVDD_IQ_INT_REF.gif
Figure 18. FF / PA Mode IOVDD Supply Current versus Voltage with Internal Reference
DAC8742H D020_SBAS856_PAFF_NoFilter_Transient.gif
Figure 20. Typical Manchester Encoded Trapezoid, No Filter
DAC8742H D025_SBAS856_MOD_OUT_v_Rload.gif
Figure 22. MOD_OUT Voltage versus RLOAD
DAC8742H D003_SBAS856_HART_INT_BPF.gif
Figure 3. HART Mode Internal Band-Pass Filter Response
DAC8742H D005_SBAS856_PAFF_INT_BPF.gif
Figure 5. FF / PA Mode Internal Band-Pass Filter Response
DAC8742H D007_SBAS856_VREF_v_Temp.gif
Figure 7. Internal Reference Voltage versus Temperature
DAC8742H D009_SBAS856_HART_Carrier_Stop.gif
Figure 9. HART TX Carrier Stop / Decay Time
DAC8742H D011_SBAS856_HART_RX_Start.gif
Figure 11. HART RX Carrier Detect On Timing
DAC8742H D013_SBAS856_AVDD_Current_EXT_REF.gif
Figure 13. HART Mode AVDD Supply Current versus Voltage with External Reference
DAC8742H D017_SBAS856_AVDD_Current_INT_REF.gif
Figure 15. HART Mode AVDD Supply Current versus Voltage with Internal Reference
DAC8742H D015_SBAS856_PAFF_AVDD_IQ_EXT_REF.gif
Figure 17. FF / PA Mode AVDD Supply Current versus Voltage with External Reference
DAC8742H D019_SBAS856_PAFF_AVDD_IQ_INT_REF.gif
Figure 19. FF / PA Mode AVDD Supply Current versus Voltage with Internal Reference
DAC8742H D021_SBAS856_PAFF_w_Filter_Transient.gif
Figure 21. Typical Manchester Encoded Trapezoid, with Suggested Filter Response