JAJSGM3 December   2018 DAC8742H

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  HART Modulator
      2. 7.3.2  HART Demodulator
      3. 7.3.3  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Encoder
      4. 7.3.4  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Decoder
      5. 7.3.5  Internal Reference
      6. 7.3.6  Clock Configuration
      7. 7.3.7  Reset and Power-Down
      8. 7.3.8  Full-Duplex Mode
      9. 7.3.9  I/O Selection
      10. 7.3.10 Jabber Inhibitor
    4. 7.4 Device Functional Modes
      1. 7.4.1 UART Interfaced HART
      2. 7.4.2 UART Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
      3. 7.4.3 SPI Interfaced HART
      4. 7.4.4 SPI Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
      5. 7.4.5 Interface
        1. 7.4.5.1 UART
          1. 7.4.5.1.1 UART Carrier Detect
        2. 7.4.5.2 SPI
          1. 7.4.5.2.1 SPI Cyclic Redundancy Check
          2. 7.4.5.2.2 SPI Interrupt Request
    5. 7.5 Register Maps
      1. 7.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 4. CONTROL Register Field Descriptions
      2. 7.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 5. RESET Register Field Descriptions
      3. 7.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 6. MODEM_STATUS Register Field Descriptions
      4. 7.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 7. MODEM_IRQ_MASK Register Field Descriptions
      5. 7.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 8. MODEM_CONTROL Register Field Descriptions
      6. 7.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 9. FIFO_D2M Register Field Descriptions
      7. 7.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 10. FIFO_M2D Register Field Descriptions
      8. 7.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 11. FIFO_LEVEL_SET Register Field Descriptions
      9. 7.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 12. PAFF_JABBER Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Design Recommendations
      2. 8.1.2 Selecting the Crystal/Resonator
      3. 8.1.3 Included Functions and Filter Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DAC8742H HART Modem
        2. 8.2.2.2 2-Wire Current Loop
        3. 8.2.2.3 Regulator
        4. 8.2.2.4 DAC
        5. 8.2.2.5 Amplifiers
        6. 8.2.2.6 Diodes
        7. 8.2.2.7 Passives
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]

The modem status register is a read/write register. When an event occurs, the corresponding bit to indicate that event is set to a logic 1 in this register. The status bits are sticky, meaning they are not cleared unless a 1 is written to the corresponding bit position, except for carrier detect, or CD, which responds based on the presences of a carrier, the FIFO level registers, which respond based on the conditions of the FIFOs, and JAB_OFF and JAB_ON which represent the current status of the jabber inibhior. CTS will assert after RTS is set and no carrier is present if not operating in full-duplex mode.

MODEM_STATUS is shown in Figure 25 and described in Table 6.

Return to Summary Table.

Figure 25. MODEM_STATUS Register
15 14 13 12 11 10 9 8
RST JAB_OFF JAB_ON GAP FRAME PARITY WDT CRC
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
FIFO_M2D LEVEL FIFO_M2D FULL FIFO_M2D EMPTY FIFO_D2M LEVEL FIFO_D2M FULL FIFO_D2M EMPTY CD CTS
R/W R/W R/W R/W R/W R/W R R

Table 6. MODEM_STATUS Register Field Descriptions

Bit Field Type Reset Description
15 RST R/W 0 A reset has occurred
14 JAB_OFF R/W 0 This bit goes high when the jabber inhibitor timeout period has expired
13 JAB_ON R/W 0 This bit goes high when the jabber inhibitor has been triggered
12 GAP R/W 0 A gap error in HART mode
11 FRAME R/W 0 A frame error in HART mode or a 1/2 bit slip in FF/PA mode
10 PARITY R/W 0 A Parity error in HART mode
9 WDT R/W 0 The watch-dog timer has expired
8 CRC R/W 0 An incorrect CRC word was provided in a read or write command
7 FIFO_M2D_LEVEL R/W 0 The receive FIFO is at the programmed level
6 FIFO_M2D_FULL R/W 0 The receive FIFO is full
5 FIFO_M2D_EMPTY R/W 0 The receive FIFO is empty
4 FIFO_D2M_LEVEL R/W 0 The transmit FIFO is at the programmed level
3 FIFO_D2M_FULL R/W 0 The transmit FIFO is full
2 FIFO_D2M_EMPTY R/W 0 The transmit FIFO is empty
1 CD R 0 In HART mode, a valid carrier has been detected
0 CTS R 0 In HART mode, the modem is cleared to send data and the modulator is active