JAJSGM3 December   2018 DAC8742H

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  HART Modulator
      2. 7.3.2  HART Demodulator
      3. 7.3.3  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Encoder
      4. 7.3.4  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Decoder
      5. 7.3.5  Internal Reference
      6. 7.3.6  Clock Configuration
      7. 7.3.7  Reset and Power-Down
      8. 7.3.8  Full-Duplex Mode
      9. 7.3.9  I/O Selection
      10. 7.3.10 Jabber Inhibitor
    4. 7.4 Device Functional Modes
      1. 7.4.1 UART Interfaced HART
      2. 7.4.2 UART Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
      3. 7.4.3 SPI Interfaced HART
      4. 7.4.4 SPI Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
      5. 7.4.5 Interface
        1. 7.4.5.1 UART
          1. 7.4.5.1.1 UART Carrier Detect
        2. 7.4.5.2 SPI
          1. 7.4.5.2.1 SPI Cyclic Redundancy Check
          2. 7.4.5.2.2 SPI Interrupt Request
    5. 7.5 Register Maps
      1. 7.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 4. CONTROL Register Field Descriptions
      2. 7.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 5. RESET Register Field Descriptions
      3. 7.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 6. MODEM_STATUS Register Field Descriptions
      4. 7.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 7. MODEM_IRQ_MASK Register Field Descriptions
      5. 7.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 8. MODEM_CONTROL Register Field Descriptions
      6. 7.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 9. FIFO_D2M Register Field Descriptions
      7. 7.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 10. FIFO_M2D Register Field Descriptions
      8. 7.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 11. FIFO_LEVEL_SET Register Field Descriptions
      9. 7.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 12. PAFF_JABBER Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Design Recommendations
      2. 8.1.2 Selecting the Crystal/Resonator
      3. 8.1.3 Included Functions and Filter Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DAC8742H HART Modem
        2. 8.2.2.2 2-Wire Current Loop
        3. 8.2.2.3 Regulator
        4. 8.2.2.4 DAC
        5. 8.2.2.5 Amplifiers
        6. 8.2.2.6 Diodes
        7. 8.2.2.7 Passives
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

PBS Package
32-Pin TQFP
Top View
DAC8742H sbas856_dac8742H_pin_diagram.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
XEN 2 Digital Input Crystal Oscillator Enable. Logic low on this pin enables the crystal oscillator circuit; in this mode an external crystal is required. Logic high on this pin disables the internal crystal oscillator circuit; in this mode an external CMOS clock or the internal oscillator are required. No digital input pin should be left floating.
CLKO 3 Digital Output Clock Output. If using the internal oscillator or an external crystal, this pin can be configured as a clock output.
CLK_CFG0 4 Digital Input Clock Configuration Pin. This pin is used to configure the input/output clocking scheme. No digital input pin should be left floating.
CLK_CFG1 5 Digital Input Clock Configuration Pin. This pin is used to configure the input/output clocking scheme. No digital input pin should be left floating.
RST 6 Digital Input Reset. Logic low on this pin places the DAC8742H into power-down mode and resets the device. Logic high returns the device to normal operation. No digital input pin should be left floating.
CD / IRQ 7 Digital Output UART Mode HART Mode Carrier detect. A logic high on this pin indicates a valid carrier is present.
FF / PA Mode While not transmitting, a logic high on this pin indicates a valid carrier is present. While transmitting, a logic high on this pin indicates that the jabber inhibitor has triggered.
SPI Mode Digital Interrupt. The interrupt can be configured as edge sensitive or level sensitive with positive or negative polarity, as set by the CONTROL register. Events that trigger an interrupt are controlled by the Modem IRQ Mask register.
IF_SEL 9 Digital Input Interface select. A logic high on this pin configures the device for SPI mode. A logic low on this pin configures the device for UART mode. An internal pull-down resistor is included. No digital input pin should be left floating.
UART_IN /
CS 		10 Digital Input UART Mode UART data input.
SPI Mode SPI chip-select. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in a high-impedance state and data on SDI are ignored. No digital input pin should be left floating. No digital input pin should be left floating.
UART_RTS /
SCLK		 11 Digital Input,
Digital Output		 UART Mode HART Mode Request to send a logic high on this pin enables the demodulator and disables the modulator. A logic low on this pin enables the modulator and disables the demodulator. No digital input pin should be left floating.
FF / PA Mode This pin reports transmit FIFO threshold information as programmed by the packet initiation code.
SPI Mode SPI clock. Data can be transferred at rates up to 12.5MHz. Schmitt-Trigger logic input.
DUPLEX / SDI 12 Digital Output UART Mode Digital input. Logic high enables full-duplex, or internal loop-back, test mode.
SPI Mode SPI data input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input. Schmitt-Trigger logic input.
UART_OUT /
SDO		 13 Digital Output UART Mode UART data output.
SPI Mode SPI data output. Data is valid on the falling edge of SCLK.
IOVDD 14 Supply Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interface.
GND 15 Supply Digital ground. Ground reference voltage for all digital circuitry of the device.
REG_CAP 18 Analog Output Capacitor for internal regulator.
MOD_OUT 19 Analog Output Modem output. FSK output sinusoid in HART mode or Manchester coded data stream in FOUNDATION Fieldbus and PROFIBUS PA modes. Requires parallel capacitance of 5-22 nF in HART mode or 0-100 pF in FOUNDATION Fieldbus and PROFIBUS PA mode for stability.
REF 20 Analog Input
or Output		 When the internal reference is enabled this pin outputs the internal reference voltage. When the internal reference is disabled, this is the external 2.5V reference input.
MOD_IN 21 Analog Input HART FSK input or FOUNDATION Fieldbus and PROFIBUS PA Manchester coded data stream input. If an external filter is used, do not connect this pin.
MOD_INF 22 Analog Input If using the internal band-pass filter, connect 680 pF to this pin or 120 pF in FOUNDATION Fieldbus and PROFIBUS PA modes. If using an external filter, connect the output of that filter to this pin.
AVDD 23 Supply Power supply.
GND 26 Supply Analog ground. Ground reference voltage for power supply input.
X2 27 Analog Input Crystal stimulus.
X1 28 Analog Input Crystal/Clock input.
GND 29 Supply Digital ground. Ground reference voltage for all digital circuitry of the device.
REF_EN 30 Digital Input Reference enable. Logic high enables the internal 1.5V reference. No digital input pin should be left floating.
BPF_EN 31 Digital Input Filter enable. A logic high enables the internal band-pass filter. No digital input pin should be left floating.
NC 1, 8, 16, 17,
24, 25, 32		 – Do not connect these pins.