JAJSES9 February 2018 DAC8771
PRODUCTION DATA.
When the RESET pin is low, the device is in hardware reset. All the analog outputs (VOUT_A to VOUT_D and IOUT_A to IOUT_D), all the registers except the POC register, and the DAC latches are set to the default reset values. In addition, the Gain and Zero Registers are loaded with default values, communication is disabled, and the signals on SYNC and SDIN are ignored (note that SDO is in a high-impedance state). When the RESET pin is high, the serial interface returns to normal operation and all the analog outputs (VOUT_A to VOUT_D and IOUT_A to IOUT_D) maintain the reset value until a new value is programmed.