JAJSES9 February 2018 DAC8771
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | IDA | IDB | IDC | CLRENA | Reserved | ||
R/W | R/W | R/W | R/W | R/W | R/W | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | REF_EN | TRN | CLR | POC | UBT | ||
R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | Reserved | R/W | 000 | Reserved |
12 | IDA | R/W | 0 | User Bit
0 - Sets this user bit low. 1 - Sets this user bit high. |
11 | IDB | R/W | 0 | User Bit
0 - Sets this user bit low. 1 - Sets this user bit high. |
10 | IDC | R/W | 0 | User Bit
0 - Sets this user bit low. 1 - Sets this user bit high. |
9 | CLREN | R/W | 0 | Clear Enable
0 - DAC hardware and software clear is disabled 1 - DAC hardware and software clear is enabled |
8:5 | Reserved | R/W | 0000 | Reserved |
4 | REF_EN | R/W | 0 | Internal reference enable/disable
0 - Internal reference disabled (default) 1 - Internal reference enabled |
3 | TRN | R/W | 0 | Enable transparent mode (see section "daisy chain operation") |
2 | CLR | R/W | 0 | Active high, clears all DAC registers to either zero or full scale based on CLSL bit. After clear completes the CLR bit resets. |
1 | POC | R/W | 0 | Power-Off-Condition
0 - IOUT to HIZ, VOUT to 30K-to-PBKG at power up, hardware or software reset (default) 1 - IOUT and VOUT to HIZ at power up, hardware and software reset |
0 | UBT | R/W | 0 | User Bit - This bit can be used to check if the communication to the chip is working correctly by writing a known value to this bit and reading that value from the status register toggle bit. The toggle resister bit UTGL (address 0x0B) is set to the same value as the UBT bit. |