JAJSES9 February 2018 DAC8771
PRODUCTION DATA.
NAME | NUMBER | TYPE | DESCRIPTION |
---|---|---|---|
AVDD | 2 | Supply | Power supply for all analog circuitry of the device except buck-boost converter and output amplifiers. |
GND | 3, 9, 18, 20, 28 | Supply | Ground. |
REFOUT | 4 | Analog Output | Internal reference output. Connects to REFIN when using internal reference. |
REFIN | 5 | Analog Input | Reference input. Connects to REFOUT when using internal reference. |
DVDD_EN | 6 | Digital Input | Internal power-supply enable pin. Connect this pin to GND to disable the internal DVDD, or leave this pin unconnected to enable the internal DVDD. When this pin is connected to GND an external supply must be connected to the DVDD pin. |
DVDD | 7 | Supply | Digital supply pin (Input/Output). Internal DVDD enabled when DVDD_EN is floating, External DVDD must be supplied when DVDD_EN is connected to GND. |
VNEG_IN | 11, 27 | Supply | Negative power supply for output stage. Connected internally, however both external connections are required. |
PVDD | 14 | Supply | Buck-Boost converter power supply. |
LP | 15 | Analog Output | External inductor positive terminal. |
PVSS | 16 | Supply | Switch ground for Buck-Boost converter. |
LN | 17 | Analog Output | External inductor negative terminal. |
VPOS_IN | 23 | Supply | Positive power supply for output stage. |
VOUT | 25 | Analog Output | Voltage output pin. |
IOUT | 26 | Analog Output | Current output pin. |
VSENSEP | 29 | Analog Input | Positive sense pin for voltage output. |
VSENSEN | 30 | Analog Input | Negative sense pin for voltage output. |
CCOMP | 31 | Analog Output | External compensation capacitor connection pin for voltage output. Addition of the external capacitor improves stability for high capacitive loads at the VOUT pin by reducing the bandwidth of the output amplifier at the expense of settling time. |
HART_IN | 32 | Analog Input | Input pin for HART modulation. If this pin is used it must be AC coupled to the HART input sinusoidal waveforms via a capacitor. If this feature is not used TI recommends to AC couple this pin to ground via a capacitor, though it may also be left floating. |
SDO | 38 | Digital Output | Serial data output. Data is valid on the falling edge of SCLK. |
SDIN | 39 | Digital Input | Serial data input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input. Schmitt-Trigger logic input. |
SCLK | 40 | Digital Input | Serial clock input of serial peripheral interface (SPI™). Data can be transferred at rates up to 25 MHz. Schmitt-Trigger logic input. |
SYNC | 41 | Digital Input | SPI™ bus chip select input (active low). Data bits are not clocked into the serial shift register unless SYNC is low. When SYNC is high SDO is in a high-impedance state. |
LDAC | 42 | Digital Input | Load DAC latch control input. A logic low on this pin loads the input shift register data into the DAC register and updates the DAC output. |
CLR | 43 | Digital Input | Level triggered clear pin (active high). Clears DAC output to zero code or mid code (see DAC Clear section). |
RESET | 44 | Digital Input | Reset input (active low). Logic low on this pin causes the device to perform a reset. |
ALARM | 45 | Digital Output | ALARM pin. Open drain output. External pull-up resistor required (10 kΩ). The pin goes low (active) when any ALARM condition is detected (open-circuit, over-temperature, watchdog timeout, and others). |
NC | 1, 8, 10, 12, 13, 19, 21, 24, 36, 37, 46, 47, 48 | N/A | No connection is required on these pins. |
DNC | 22,33, 34, 35 | N/A | Do not connect these pins. |