DAC8812 Dual, Serial-Input 16-Bit Multiplying Digital-to-Analog Converter
- SBAS349F August 2005 – June 2016 DAC8812
  
  PRODUCTION DATA.

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DATA SHEET

DAC8812 Dual, Serial-Input 16-Bit Multiplying Digital-to-Analog Converter

1 Features

Relative Accuracy: 1 LSB Max
Differential Nonlinearity: 1 LSB Max
2-mA Full-Scale Current ±20%,
With V_REF = ±10 V
0.5-μs Settling Time
Midscale or Zero-Scale Reset
Separate 4Q Multiplying Reference Inputs
Reference Bandwidth: 10 MHz
Reference Dynamics: –105-dB THD
SPI™-Compatible 3-Wire Interface:
50 MHz
Double Buffered Registers to Enable
Simultaneous Multichannel Update
Internal Power-On Reset
Industry-Standard Pin Configuration

2 Applications

Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration

3 Description

The DAC8812 is a dual, 16-bit, current-output digital-to-analog converter (DAC) designed to operate from a single 2.7-V to 5.5-V supply.

The applied external reference input voltage V_REF determines the full-scale output current. An internal feedback resistor (R_FB) provides temperature tracking for the full-scale output when combined with an external I-to-V precision amplifier.

A double-buffered, serial data interface offers high-speed, 3-wire, SPI and microcontroller compatible inputs using serial data in (SDI), clock (CLK), and a chip-select (CS). A common level-sensitive load DAC strobe (LDAC) input allows simultaneous update of all DAC outputs from previously loaded input registers. Additionally, an internal power-on reset forces the output voltage to zero at system turnon. An MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0, or to midscale code when MSB = 1.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DAC8812	TSSOP (16)	5.00 mm × 4.40 mm

For all available packages, see the orderable addendum at the end of the data sheet.

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Functional Block Diagram

4 Revision History

Changes from E Revision (March 2016) to F Revision

Changed the maximum T_A value from 125°C to 85°C in the Recommended Operating Conditions table Go
Changed the name of the input resistance match parameter to Channel-to-channel input resistance match in the Electrical Characteristics tableGo
Made V_REF negative in the equation for V_OUTGo
Added the Receiving Notification of Documentation Updates section Go

Changes from D Revision (January 2016) to E Revision

Changed the DAC8812 Timing Diagram imageGo

Changes from C Revision (November 2015) to D Revision

Changed the DAC8812 Timing Diagram image to show the setup and hold time with respect to rising edge Go

Changes from B Revision (February 2007) to C Revision

Added ESD Ratings table, Timing Requirements and Switching Characteristics tables, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
Replaced Package/Ordering Information table with Device Comparison tableGo
Added I/O column to Pin Functions tableGo

5 Device Comparison Table

DEVICE	MAXIMUM RELATIVE ACCURACY (LSB)
DAC8812C	±1
DAC8812B	±2

6 Pin Configuration and Functions

PW Package

16-Pin TSSOP

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	R_FBA	I	Establish voltage output for DAC A by connecting to external amplifier output.
2	V_REFA	I	DAC A reference voltage input pin. Establishes DAC A full-scale output voltage. Can be tied to V_DD pin.
3	I_OUTA	O	DAC A current output
4	A_GNDA	—	DAC A analog ground
5	A_GNDB	—	DAC B analog ground
6	I_OUTB	O	DAC B current output
7	V_REFB	I	DAC B reference voltage input pin. Establishes DAC B full-scale output voltage. Can be tied to V_DD pin.
8	R_FBB	I	Establish voltage output for DAC B by connecting to external amplifier output.
9	SDI	I	Serial data input; data loads directly into the shift register.
10	RS	I	Reset pin; active-low input. Input registers and DAC registers are set to all 0s or midscale. Register data = 0x0000 when MSB = 0. Register data = 0x8000 when MSB = 1 for DAC8812.
11	CS	I	Chip-select; active-low input. Disables shift register loading when high. Transfers serial register data to input register when CS goes high. Does not affect LDAC operation.
12	DGND	—	Digital ground
13	V_DD	I	Positive power-supply input. Specified range of operation 2.7 V to 5.5 V.
14	MSB	I	MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can be permanently tied to ground or V_DD.
15	LDAC	I	Load DAC register strobe; level-sensitive active-low. Transfers all input register data to the DAC registers. Asynchronous active-low input. See Table 2 for operation.
16	CLK	I	Clock input. Positive edge clocks data into shift register.