SBAS349F August   2005  – June 2016 DAC8812

PRODUCTION DATA.  

  1. 1  Features
  2. 2  Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
      1. 7.8.1 Channel A—5 V
      2. 7.8.2 Channel B—5 V
      3. 7.8.3 Channel A and B—5 V
      4. 7.8.4 Channel A—2.7 V
      5. 7.8.5 Channel B—2.7 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converters
      2. 8.3.2 Power-On Reset
        1. 8.3.2.1 ESD Protection Circuits
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Data Interface
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD to GND –0.3 7 V
VREFx, RFBx to GND –18 18 V
Digital logic inputs to GND –0.3 VDD + 0.3 V
IOUTx to GND –0.3 VDD + 0.3 V
AGNDx to DGND –0.3 0.3 V
Input current to any pin except supplies –50 50 mA
Package power dissipation (TJmax – TA) / RθJA W
Maximum junction temperature (TJmax) 150 °C
Operating temperature –40 85 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±4000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage to GND 2.7 5.5 V
TA Operating ambient temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) DAC8812 UNIT
PW (TSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 100.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.8 °C/W
RθJB Junction-to-board thermal resistance 46.8 °C/W
ψJT Junction-to-top characterization parameter 2 °C/W
ψJB Junction-to-board characterization parameter 46 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

VDD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA,B = 10 V, TA = full operating temperature range, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution 16 Bits
INL Relative accuracy DAC8812B ±2 LSB
DAC8812C ±1
DNL Differential nonlinearity ±1 LSB
IOUTx Output leakage current Data = 0000h, TA = 25°C 10 nA
Data = 0000h, TA = TA max 20
GFSE Full-scale gain error Data = FFFFh ±0.75 ±4 mV
TCVFS Full-scale temperature coefficient(2) 1 ppm/°C
RFBX Feedback resistor VDD = 5 V 5 kΩ
REFERENCE INPUT(2)
VREFx VREFx range –15 15 V
RREFx Input resistance 4 5 6 kΩ
Channel-to-channel input resistance match 1%
CREFx Input capacitance 5 pF
ANALOG OUTPUT(2)
IOUTx Output current Data = FFFFh 1.6 2.5 mA
COUTx Output capacitance Code-dependent 50 pF
LOGIC INPUTS(2)
VIL Input low voltage VDD = 2.7 V 0.6 V
VDD = 5 V 0.8
VIH Input high voltage VDD = 2.7 V 2.1 V
VDD = 5 V 2.4
IIL Input leakage current 1 μA
CIL Input capacitance 10 pF
SUPPLY CHARACTERISTICS
VDD RANGE Power supply range 2.7 5.5 V
IDD Positive supply current Logic inputs = 0 V, VDD = 4.5 V to 5.5 V 2 5 μA
Logic inputs = 0 V, VDD = 2.7 V to 3.6 V 1 2.5 μA
PDISS Power dissipation Logic inputs = 0 V 0.0275 mW
PSS Power supply sensitivity ΔVDD = ±5% 0.006%
AC CHARACTERISTICS(2) (3)
ts Output voltage settling time To ±0.1% of full-scale,
Data = 0000h to FFFFh to 0000h		 0.3 µs
To ±0.0015% of full-scale,
Data = 0000h to FFFFh to 0000h		 0.5
QG DAC glitch impulse Data = 7FFFh to 8000h to 7FFFh 5 nV-s
BW –3 dB Reference multiplying BW VREFx = 100 mVRMS, Data = FFFFh, CFB = 3 pF 10 MHz
Feedthrough error Data = 0000h, VREFx = 100 mVRMS, f = 100 kHz –70 dB
Crosstalk error Data = 0000h, VREFB = 100 mVRMS,
Adjacent channel, f = 100 kHz		 –100 dB
QD Digital feedthrough CS = 1 and fCLK = 1 MHz 1 nV-s
THD Total harmonic distortion VREF = 5 VPP, Data = FFFFh, f = 1 kHz –105 dB
en Output spot noise voltage f = 1 kHz, BW = 1 Hz 12 nV/√Hz
(1) All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OPA277 I-to-V converter amplifier. The DAC8812 RFB pin is tied to the amplifier output. Typical values represent average readings measured at 25°C.
(2) These parameters are not subject to production testing.
(3) All ac characteristic tests are performed in a closed-loop system using a THS4011 I-to-V converter amplifier.

7.6 Timing Requirements

See Figure 1
MIN NOM MAX UNIT
INTERFACE TIMING(1)
tCH Clock duration, high 10 ns
tCL Clock duration, low 10 ns
tCSS CS to clock setup 0 ns
tCSH Clock to CS hold 10 ns
tLDAC Load DAC pulse duration 20 ns
tDS Data setup 10 ns
tDH Data hold 10 ns
tLDS Load setup 5 ns
tLDH Load hold 25 ns
(1) All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

7.7 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERFACE TIMING
tPD Clock to SDO propagation delay 2 20 ns
DAC8812 timing_SBAS349.gif Figure 1. DAC8812 Timing Diagram

7.8 Typical Characteristics

7.8.1 Channel A—5 V

At TA = 25°C, VDD = 5 V, unless otherwise noted
DAC8812 tc_5v_cha_25c_inl_bas349.gif
Figure 2. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_5v_cha_-40c_inl_bas349.gif
Figure 4. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_5v_cha_85c_inl_bas349.gif
Figure 6. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_5v_cha_25c_dnl_bas349.gif
Figure 3. Differential Nonlinearity vs Digital Input Code
DAC8812 tc_5v_cha_-40c_dnl_bas349.gif
Figure 5. Differential Nonlinearity vs Digital Input Code
DAC8812 tc_5v_cha_85c_dnl_bas349.gif
Figure 7. Differential Nonlinearity vs Digital Input Code

7.8.2 Channel B—5 V

At TA = 25°C, VDD = 5 V, unless otherwise noted
DAC8812 tc_5v_chb_25c_inl_bas349.gif
Figure 8. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_5v_chb_-40c_inl_bas349.gif
Figure 10. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_5v_chb_85c_inl_bas349.gif
Figure 12. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_5v_chb_25c_dnl_bas349.gif
Figure 9. Differential Nonlinearity vs Digital Input Code
DAC8812 tc_5v_chb_-40c_dnl_bas349.gif
Figure 11. Differential Nonlinearity vs Digital Input Code
DAC8812 tc_5v_chb_85c_dnl_bas349.gif
Figure 13. Differential Nonlinearity vs Digital Input Code

7.8.3 Channel A and B—5 V

At TA = 25°C, VDD = 5 V, unless otherwise noted
DAC8812 tc_idd_v_logic_bas349.gif
Figure 14. Supply Current vs Logic Input Voltage
DAC8812 tc_dac-glitch_bas349.gif
Figure 16. DAC Glitch
DAC8812 ref_bw_bas349.gif
Figure 15. Reference Multiplying Bandwidth
DAC8812 tc_dac-settling_bas349.gif
Figure 17. DAC Settling Time

7.8.4 Channel A—2.7 V

At TA = 25°C, VDD = 2.7 V, unless otherwise noted
DAC8812 tc_27v_cha_25c_inl_bas349.gif
Figure 18. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_27v_cha_-40c_inl_bas349.gif
Figure 20. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_27v_cha_85c_inl_bas349.gif
Figure 22. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_27v_cha_25c_dnl_bas349.gif
Figure 19. Differential Nonlinearity vs Digital Input Code
DAC8812 tc_27v_cha_-40c_dnl_bas349.gif
Figure 21. Differential Nonlinearity vs Digital Input Code
DAC8812 tc_27v_cha_85c_dnl_bas349.gif
Figure 23. Differential Nonlinearity vs Digital Input Code

7.8.5 Channel B—2.7 V

At TA = 25°C, VDD = 2.7 V, unless otherwise noted
DAC8812 tc_27v_chb_25c_inl_bas349.gif
Figure 24. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_27v_chb_-40c_inl_bas349.gif
Figure 26. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_27v_chb_85c_inl_bas349.gif
Figure 28. Integral Nonlinearity vs Digital Input Code
DAC8812 tc_27v_chb_25c_dnl_bas349.gif
Figure 25. Differential Nonlinearity vs Digital Input Code
DAC8812 tc_27v_chb_-40c_dnl_bas349.gif
Figure 27. Differential Nonlinearity vs Digital Input Code
DAC8812 tc_27v_chb_85c_dnl_bas349.gif
Figure 29. Differential Nonlinearity vs Digital Input Code