JAJS261B July   2007  – January 2018 DAC8881

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics for
    7. 6.7 Timing Characteristics for and
    8. 6.8 Typical Characteristics: VDD = +5 V
    9. 6.9 TYpical Characteristics: VDD = +2.7 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Output
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Output Range
      4. 7.3.4  Input Data Format
      5. 7.3.5  Hardware Reset
      6. 7.3.6  Power-On Reset
      7. 7.3.7  Program Reset Value
      8. 7.3.8  Power Down
      9. 7.3.9  Double-Buffered Interface
      10. 7.3.10 Load DAC Pin (LDAC)
        1. 7.3.10.1 Synchronous Mode
        2. 7.3.10.2 Asynchronous Mode
      11. 7.3.11 1.8 V to 5.5 V Logic Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
        1. 7.4.1.1 Input Shift Register
          1. 7.4.1.1.1 Stand-Alone Mode
          2. 7.4.1.1.2 Daisy-Chain Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using The DAC8881
    2. 8.2 Typical Application
      1. 8.2.1 DAC8881 Sample Hold Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

All specifications at TA = TMIN to TMAX, AVDD = DVDD = +2.7 V to +5.5 V, IOVDD = +1.8 V to +5.5 V, gain = 1X mode, unless otherwise noted.
PARAMETER CONDITIONS DAC8881 UNIT
MIN TYP MAX
ACCURACY
Linearity error Measured by line passing through codes 0200h and FE00h ±0.5 ±1 LSB
Differential linearity error Measured by line passing through codes 0200h and FE00h ±0.25 ±1 LSB
Monotonicity 16 Bits
Zero-scale error TA = +25°C, code = 0200h ±4 LSB
TMIN to TMAX, code = 0200h ±8 LSB
Zero-scale drift Code = 0200h ±0.5 ±1 ppm/°C of FSR
Gain error TA = +25°C, Measured by line passing through codes 0200h and FE00h ±4 ±8 LSB
Gain temperature drift Measured by line passing through codes 0200h and FE00h ±0.5 ±1 ppm/°C
PSRR VOUT = full-scale, AVDD = +5 V ±10% 2 LSB/V
ANALOG OUTPUT(2)
Voltage output(1) 0 AVDD V
Output voltage drift vs time Device operating for 500 hours 5 ppm of FSR
Device operating for 1000 hours 8 ppm of FSR
Output current 2.5 mA
Maximum load capacitance 200 pF
Short-circuit current +31, –50 mA
REFERENCE INPUT(2)
VREFH input voltage range AVDD = +5.5 V 1.25 5.0 AVDD V
AVDD = +3 V 1.25 2.5 AVDD V
VREFH input capacitance 5 pF
VREFH input impedance 4.5 kΩ
VREFL input voltage range –0.2 0 +0.2 V
VREFL input capacitance 4.5 pF
VREFL input impedance 5 kΩ
DYNAMIC PERFORMANCE(2)
Settling time To ±0.003% FS, RL = 10 kΩ, CL = 50 pF, code 1000h to F000h 5 μs
Slew rate From 10% to 90% of 0 V to +5 V 2.5 V/μs
Code change glitch Code = 7FFFh to 8000h to 7FFFh VREFH = 5 V, gain = 1X mode 37 nV-s
VREFH = 2.5 V, gain = 1X mode 18 nV-s
VREFH = 1.25 V, gain = 1X mode 9 nV-s
VREFH = 2.5 V, gain = 2X mode 21 nV-s
VREFH = 1.25 V, gain = 2X mode 10 nV-s
Digital feedthrough 1 nV-s
Output noise voltage density f = 1 kHz to 100 kHz,
full-scale output		 Gain = 1 24 30 nV/√Hz
Gain = 2 40 48 nV/√Hz
Output noise voltage f = 0.1Hz to 10Hz, full-scale output 2 μVPP
DIGITAL INPUTS(2)
High-level input voltage, VIH IOVDD = 4.5 V to 5.5 V 3.8 IOVDD + 0.3 V
IOVDD = 2.7 V to 3.3 V 2.1 IOVDD + 0.3 V
IOVDD = 1.7 V to 2 V 1.5 IOVDD + 0.3 V
Low-level input voltage, VIL IOVDD = 4.5 V to 5.5 V –0.3 0.8 V
IOVDD = 2.7 V to 3.3 V –0.3 0.6 V
IOVDD = 1.7 V to 2 V –0.3 0.3 V
Digital input current (IIN) ±1 ±10 μA
Digital input capacitance 5 pF
DIGITAL OUTPUT(2)
High-level output voltage, VOH IOVDD = 2.7 V to 5.5 V, IOH = –1 mA IOVDD – 0.2 V
IOVDD = 1.7 V to 2 V, IOH = –500 μA IOVDD – 0.2 V
Low-level output voltage, VOL IOVDD = 2.7 V to 5.5 V, IOL = 1 mA 0.2 V
IOVDD = 1.7 V to 2 V, IOL = 500 μA 0.2 V
POWER SUPPLY
AVDD +2.7 +5.5 V
DVDD +2.7 +5.5 V
IOVDD +1.7 DVDD V
AIDD VIH = IOVDD, VIL = DGND 1.5 mA
DIDD VIH = IOVDD, VIL = DGND 1 10 μA
IOIDD VIH = IOVDD, VIL = DGND 1 10 μA
AIDD power-down PDN = IOVDD 25 50 μA
Power dissipation AVDD = DVDD = 5.0V 6 7.5 mW
TEMPERATURE RANGE
Specified performance –40 +105 °C
(1) The output from the VOUT pin = [(VREFH – VREFL)/65536] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0 V to AVDD. The full-scale of the output must be less than AVDD; otherwise, output saturation occurs.
(2) Specified by design. Not production tested.