JAJS261B July   2007  – January 2018 DAC8881

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics for
    7. 6.7 Timing Characteristics for and
    8. 6.8 Typical Characteristics: VDD = +5 V
    9. 6.9 TYpical Characteristics: VDD = +2.7 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Output
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Output Range
      4. 7.3.4  Input Data Format
      5. 7.3.5  Hardware Reset
      6. 7.3.6  Power-On Reset
      7. 7.3.7  Program Reset Value
      8. 7.3.8  Power Down
      9. 7.3.9  Double-Buffered Interface
      10. 7.3.10 Load DAC Pin (LDAC)
        1. 7.3.10.1 Synchronous Mode
        2. 7.3.10.2 Asynchronous Mode
      11. 7.3.11 1.8 V to 5.5 V Logic Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
        1. 7.4.1.1 Input Shift Register
          1. 7.4.1.1.1 Stand-Alone Mode
          2. 7.4.1.1.2 Daisy-Chain Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using The DAC8881
    2. 8.2 Typical Application
      1. 8.2.1 DAC8881 Sample Hold Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 TYpical Characteristics: VDD = +2.7 V

At TA = +25°C, VREFH = +2.5 V, VREFL = 0 V, and Gain = 1X Mode, unless otherwise noted.

DAC8881 tc_27v_25c_inl_bas422.gifFigure 44. Linearity Error vs Digital Input Code
DAC8881 tc_27v_40c_inl_bas422.gifFigure 46. Linearity Error vs Digital Input Code
DAC8881 tc_27v_105c_inl_bas422.gifFigure 48. Linearity Error vs Digital Input Code
DAC8881 tc_27v_inl-vref_bas422.gifFigure 50. Linearity Error vs
DAC8881 tc_27v_is-tmp_bas422.gifFigure 52. AVDD Supply Current vs Temperature
DAC8881 tc_27v_iref-code_2x_bas422.gifFigure 54. Reference Current vs Digital Input Code
(Gain = 2X Mode)
DAC8881 tc_27v_vo-dcc_avdd_bas422.gifFigure 56. Output Voltage vs Drive Current Capability
(Operation Near AVDD Rail)
DAC8881 tc_27v_time_0-f_bas422.gifFigure 58. Large Signal Settling Time
DAC8881 tc_27v_time_1-f_bas422.gifFigure 60. Large Signal Settling Time
DAC8881 tc_27v_glch_7-8_25v_bas422.gifFigure 62. Major Carry Glitch
DAC8881 tc_27v_glch_7-8_125v_bas422.gifFigure 64. Major Carry Glitch
DAC8881 tc_27v_25c_dnl_bas422.gifFigure 45. Differential Linearity Error vs Digital Input Code
DAC8881 tc_27v_40c_dnl_bas422.gifFigure 47. Differential Linearity Error vs Digital Input Code
DAC8881 tc_27v_105c_dnl_bas422.gifFigure 49. Differential Linearity Error vs Digital Input Code
DAC8881 tc_27v_dnl-vref_bas422.gifFigure 51. Differential Linearity Error vs Reference Voltage
DAC8881 tc_27v_iref-code_bas422.gifFigure 53. Reference Current vs Digital Input Code
DAC8881 tc_27v_vo-dcc_bas422.gifFigure 55. Output Voltage vs Drive Current Capability
DAC8881 tc_27v_vo-dcc_agnd_bas422.gifFigure 57. Output Voltage vs Drive Current Capability
(Operation Near AGND Rail)
DAC8881 tc_27v_time_f-0_bas422.gifFigure 59. Large Signal Settling Time
DAC8881 tc_27v_time_f-1_bas422.gifFigure 61. Large Signal Settling Time
DAC8881 tc_27v_glch_8-7_25v_bas422.gifFigure 63. Major Carry Glitch
DAC8881 tc_27v_glch_8-7_125v_bas422.gifFigure 65. Major Carry Glitch