JAJSI70C May   2008  – November 2019 DAC9881

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: AVDD = 5 V
    6. 7.6  Electrical Characteristics: AVDD = 2.7 V
    7. 7.7  Timing Requirements—Standalone Operation Without SDO
    8. 7.8  Timing Requirements—Standalone Operation With SDO and Daisy-Chain Mode
    9. 7.9  Typical Characteristics: AVDD = 5 V
    10. 7.10 Typical Characteristics: AVDD = 2.7 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Output
      2. 8.3.2  Reference Inputs
      3. 8.3.3  Output Range
      4. 8.3.4  Input Data Format
      5. 8.3.5  Hardware Reset
      6. 8.3.6  Power-On Reset
        1. 8.3.6.1 Program Reset Value
      7. 8.3.7  Power Down
      8. 8.3.8  Double-Buffered Interface
        1. 8.3.8.1 Load DAC Pin (LDAC)
          1. 8.3.8.1.1 Synchronous Mode
          2. 8.3.8.1.2 Asynchronous Mode
      9. 8.3.9  1.8-V to 5-V Logic Interface
      10. 8.3.10 Power-Supply Sequence
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface
        1. 8.4.1.1 Input Shift Register
          1. 8.4.1.1.1 Stand-Alone Mode
          2. 8.4.1.1.2 Daisy-Chain Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bipolar Operation Using the DAC9881
    2. 9.2 Typical Application
      1. 9.2.1 DAC9881 Sample-and-Hold Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 System Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics: AVDD = 5 V

all specifications at TA = TMIN to TMAX, AVDD = 4.75 V to 5.5 V, IOVDD = 1.8 V to 5.5 V, VREFH = 5 V, VREFL = 0 V, and gain = 1X mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ACCURACY(1)
Integral linearity error Measured by line passing through codes 2048 and 260096 DAC9881S ±2 ±3 LSB
DAC9881SB ±1 ±2 LSB
Differential linearity error Measured by line passing through codes 2048 and 260096 DAC9881S –1 ±0.75 +2 LSB
DAC9881SB ±0.5 ±1 LSB
Monotonicity 18 Bits
Zero-scale error TA = 25°C, code = 2048 ±16 LSB
TMIN to TMAX, code = 2048 ±32 LSB
Zero-scale drift(2) Code = 2048 ±0.25 ±0.8 ppm/°C of FSR
Gain error TA = 25°C, measured by line passing through codes 2048 and 260096 ±16 ±32 LSB
Gain temperature drift(2) Measured by line passing through codes 2048 and 260096 ±0.25 ±0.4 ppm/°C
PSRR(2) VOUT = full-scale, AVDD = 5 V ±10% 32 LSB/V
ANALOG OUTPUT(2)
Voltage output(3) 0 AVDD V
Output voltage drift vs time Device operating for 500 hours at 25°C 0.1 ppm of FSR
Device operating for 1000 hours at 25°C 0.2 ppm of FSR
Output current(4) 2.5 mA
Maximum load capacitance 200 pF
Short-circuit current 31/–50 mA
REFERENCE INPUT(2)
VREFH input voltage range AVDD = 5.5 V 1.25 5 AVDD V
VREFH input capacitance 5 pF
VREFH input impedance 4.5 kΩ
VREFL input voltage range –0.2 0 0.2 V
VREFL input capacitance 4.5 pF
VREFL input impedance 5 kΩ
DYNAMIC PERFORMANCE(2)
Settling time To ±0.003% FS, RL = 10 kΩ, CL = 50 pF, code 04000h to 3C000h 5 µs
Slew rate From 10% to 90% of 0 V to 5 V 2.5 V/µs
Code change glitch Code = 1FFFFh to 20000h to 1FFFFh VREFH = 5 V, gain = 1X mode 37 nV-s
VREFH = 2.5 V, gain = 1X mode 18 nV-s
VREFH = 1.25 V, gain = 1X mode 9 nV-s
VREFH = 2.5 V, gain = 2X mode 21 nV-s
VREFH = 1.25 V, gain = 2X mode 10 nV-s
Digital feedthrough CS = high, fSCLK = 1 kHz 1 nV-s
Output noise voltage density f = 1 kHz to 100 kHz,
full-scale output		 Gain = 1 24 30 nV/√Hz
Gain = 2 40 48 nV/√Hz
Output noise voltage f = 0.1 Hz to 10 Hz, full-scale output 2 µVPP
DIGITAL INPUTS(2)
High-level input voltage, VIH IOVDD = 4.5 V to 5.5 V 3.8 IOVDD + 0.3 V
IOVDD = 2.7 V to 3.3 V 2.1 IOVDD + 0.3 V
IOVDD = 1.7 V to 2 V 1.5 IOVDD + 0.3 V
Low-level input voltage, VIL IOVDD = 4.5 V to 5.5 V –0.3 0.8 V
IOVDD = 2.7 V to 3.3 V –0.3 0.6 V
IOVDD = 1.7 V to 2 V –0.3 0.3 V
Digital input current (IIN) ±1 ±10 µA
Digital input capacitance 5 pF
DIGITAL OUTPUT(2)
High-level output voltage, VOH IOVDD = 2.7 V to 5.5 V, IOH = –1 mA IOVDD – 0.2 V
IOVDD = 1.7 V to 2 V, IOH = –500 μA IOVDD – 0.2 V
Low-level output voltage, VOL IOVDD = 2.7V to 5.5 V, IOL = 1 mA 0.2 V
IOVDD = 1.7 V to 2 V, IOL = 500 μA 0.2 V
POWER SUPPLY
AVDD 4.75 5 5.5 V
IOVDD 1.7 AVDD V
AIDD VIH = IOVDD, VIL = DGND 0.85 1.5 mA
IOIDD VIH = IOVDD, VIL = DGND 1 10 µA
AIDD power-down PDN pin = IOVDD 25 50 µA
Power dissipation AVDD = 5 V 4.3 7.5 mW
(1) DAC output range is 0 V to 5 V. 1 LSB = 19 μV.
(2) Specified by design; not production tested.
(3) The output from the VOUT pin = [(VREFH – VREFL) / 262144] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0 V to AVDD. The full-scale of the output must be less than AVDD; otherwise, output saturation occurs.
(4) See Figure 26, Figure 27, and Figure 28 for details.