JAJSI70C May   2008  – November 2019 DAC9881

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: AVDD = 5 V
    6. 7.6  Electrical Characteristics: AVDD = 2.7 V
    7. 7.7  Timing Requirements—Standalone Operation Without SDO
    8. 7.8  Timing Requirements—Standalone Operation With SDO and Daisy-Chain Mode
    9. 7.9  Typical Characteristics: AVDD = 5 V
    10. 7.10 Typical Characteristics: AVDD = 2.7 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Output
      2. 8.3.2  Reference Inputs
      3. 8.3.3  Output Range
      4. 8.3.4  Input Data Format
      5. 8.3.5  Hardware Reset
      6. 8.3.6  Power-On Reset
        1. 8.3.6.1 Program Reset Value
      7. 8.3.7  Power Down
      8. 8.3.8  Double-Buffered Interface
        1. 8.3.8.1 Load DAC Pin (LDAC)
          1. 8.3.8.1.1 Synchronous Mode
          2. 8.3.8.1.2 Asynchronous Mode
      9. 8.3.9  1.8-V to 5-V Logic Interface
      10. 8.3.10 Power-Supply Sequence
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface
        1. 8.4.1.1 Input Shift Register
          1. 8.4.1.1.1 Stand-Alone Mode
          2. 8.4.1.1.2 Daisy-Chain Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Bipolar Operation Using the DAC9881
    2. 9.2 Typical Application
      1. 9.2.1 DAC9881 Sample-and-Hold Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 System Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 SCLK I SPI bus serial clock input
2 SDI I SPI bus serial data input
3 LDAC I Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the DAC latch is updated. It is recommended to connect this pin to IOVDD through a pullup resistor.
4 AGND I Analog ground
5 AVDD I Analog power supply
6 VREFL-S I Reference low input sense
7 VREFH-S I Reference high input sense
8 VOUT O Output of output buffer
9 RFB I Feedback resistor connected to the inverting input of the output buffer
10 VREFL-F I Reference low input force
11 VREFH-F I Reference high input force
12 NC — Do not connect
13 NC — Do not connect
14 RSTSEL I Selects the value of the output from the VOUT pin after power-on or hardware reset. If RSTSEL = IOVDD, then register data = 20000h. If RSTSEL = DGND, then register data = 00000h.
15 GAIN I Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to IOVDD.
16 USB/BTC I Input data format selection. Input data are straight binary format when the pin is connected to IOVDD, and in two's complement format when the pin is connected to DGND.
17 RST I Reset input (active low). Logic low on this pin causes the device to perform a reset.
18 PDN I Power-down input (active high). Logic high on this pin forces the device into power-down status. In power-down, the VOUT pin connects to AGND through a 10-kΩ resistor.
19 CS I SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is high, SDO is in a high-impedance state. It is recommended to connect this pin to IOVDD through a pullup resistor.
20 SDOSEL I SPI serial data output selection. When SDOSEL is tied to IOVDD, the contents of the existing input register are shifted out from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register are shifted out from the SDO pin; this is Daisy-Chain mode for daisy-chained communication.
21 AVDD I Analog power supply. Must be connected to pin 5.
22 DGND I Digital ground
23 SDO O SPI bus serial data output. Refer to the timing diagrams for further detail.
24 IOVDD I Interface power. Connect to 1.8 V for 1.8-V logic, 3 V for 3-V logic, and to 5 V for 5-V logic.
Thermal pad — The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible.