JAJSMO5C August   2000  – August 2021 DCV010505 , DCV010505D , DCV010512 , DCV010512D , DCV010515 , DCV010515D , DCV011512D , DCV011515D , DCV012405 , DCV012415D

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Isolation
        1. 8.3.1.1 Operation or Functional Isolation
        2. 8.3.1.2 Basic or Enhanced Isolation
        3. 8.3.1.3 Working Voltage
        4. 8.3.1.4 Isolation Voltage Rating
        5. 8.3.1.5 Repeated High-Voltage Isolation Testing
      2. 8.3.2  Power Stage
      3. 8.3.3  Oscillator and Watchdog Circuit
      4. 8.3.4  Thermal Shutdown
      5. 8.3.5  Synchronization
      6. 8.3.6  Light Load Operation (< 10%)
      7. 8.3.7  Load Regulation (10% to 100%)
      8. 8.3.8  Construction
      9. 8.3.9  Thermal Management
      10. 8.3.10 Power-Up Characteristics
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable and Enable (SYNCIN Pin)
      2. 8.4.2 Decoupling
        1. 8.4.2.1 Ripple Reduction
        2. 8.4.2.2 Connecting the DCV01 in Series
        3. 8.4.2.3 Connecting the DCV01 in Parallel
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitor
        2. 9.2.2.2 Output Capacitor
        3. 9.2.2.3 SYNCIN Pin
        4. 9.2.2.4 PCB Design
        5. 9.2.2.5 Decoupling Ceramic Capacitors
        6. 9.2.2.6 Input Capacitor and the Effects of ESR
        7. 9.2.2.7 Ripple and Noise
          1. 9.2.2.7.1 Output Ripple Calculation Example
        8. 9.2.2.8 Dual DCV01 Output Voltage
        9. 9.2.2.9 Optimizing Performance
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Device Comparison Table

at TA = 25°C, +VS = nominal, CIN = 2.2 µF, and COUT = 0.1 µF (unless otherwise noted)

DEVICE NUMBER INPUT
VOLTAGE
VS (V)		 OUTPUT
VOLTAGE
VNOM at VS (TYP) (V)
75% LOAD		 DEVICE
OUTPUT
CURRENT
(mA)(3)		 LOAD
REGULATION
10% TO 100%
LOAD(1)		 NO LOAD
CURRENT
IQ (mA)
0% LOAD		 EFFICIENCY
(%)
100% LOAD		 BARRIER
CAPACITANCE
CISO (pF)
VISO = 750 Vrms
MIN TYP MAX MIN TYP MAX MAX TYP MAX TYP TYP TYP
DCV010505P
DCV010505P-U		 4.5 5 5.5 4.75 5 5.25 200 19 31 20 80 3.6
DCV010505DP
DCV010505DP-U		 4.5 5 5.5 ±4.25 ±5 ±5.75 200(2) 18 32 22 81 3.8
DCV010512P
DCV010512P-U		 4.5 5 5.5 11.4 12 12.6 83 21 38 29 85 5.1
DCV010512DP
DCV010512DP-U		 4.5 5 5.5 ±11.4 ±12 ±12.6 83(2) 19 37 40 82 4
DCV010515P
DCV010515P-U		 4.5 5 5.5 14.25 15 15.75 66 26 42 34 82 3.8
DCV010515DP
DCV010515DP-U		 4.5 5 5.5 ±14.25 ±15 ±15.75 66(2) 19 41 42 85 4.7
DCV011512DP
DCV011512DP-U		 13.5 15 16.5 ±11.4 ±12 ±12.6 83 (2) 11 39 19 78 2.5
DCV011515DP
DCV011515DP-U		 13.5 15 16.5 ±14.25 ±15 ±15.75 66(2) 12 39 20 80 2.5
DCV012405P
DCV012405P-U		 21.6 24 26.4 4.75 5 5.25 200 13 23 14 77 2.5
DCV012415DP
DCV012415DP-U		 21.6 24 26.4 ±14.25 ±15 ±15.75 66(2) 10 35 17 76 3.8
(1) Load regulation = (VOUT at 10% load – VOUT at 100%)/VOUT at 75% load
(2) IOUT1 + IOUT2
(3) POUT(max) = 1 W