JAJSVE5 データシート

JAJSVE5 September 2024 DDS39RF12 , DDS39RFS12

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

ACL|256
- MPBGAY8
ACK|256
- MPBGAW1B

サーマルパッド・メカニカル・データ

発注情報

7.5.3 SPI Register Map

Table 7-32 lists the SPI registers. All register offset addresses not listed in Table 7-32 should be considered as reserved locations and the register contents should not be modified. Reserved register fields in addresses with non-reserved R/W fields always return the default/reset value during read, not the written value.

Table 7-32 SPI Registers

Offset	Acronym	Register Name	Section
0x0000	CONFIG_A	Configuration A	Go
0x0002	DEVICE_CONFIG	Device Configuration	Go
0x0003	CHIP_TYPE	Chip Type	Go
0x0004	CHIP_ID	Chip Identification	Go
0x0006	CHIP_VERSION	Chip Version	Go
0x000C	VENDOR_ID	Vendor Identification	Go
0x0010-0x007F	RESERVED
0x0080	SYSREF_CTRL	SYSREF Control	Go
0x0081-0x008F	RESERVED
0x0090-0x0092	SYSREF_POS	SYSREF Capture Position	Go
0x0093-0x009F	RESERVED
0x00A0	SYSREF_ALIGN	SYSREF Alignment Control	Go
0x00A1	SYSREF_TERM	SYSREF Termination Configuration	Go
0x00A2-0x00FF	RESERVED
0x0100	JESD_EN	JESD204C Subsystem Enable	Go
0x0101	JMODE	JESD204C Mode	Go
0x0102	JESD_M	JESD204C Number of Streams	Go
0x0103	JCTRL	JESD204C Control	Go
0x0104	SHMODE	JESD204C Sync Word Mode	Go
0x0105	KM1	JESD204C K Parameter	Go
x0106	RBD	JESD204C Release Buffer Delay	Go
0x0107	JESD_STATUS	JESD204C System Status Register	Go
0x0108	REFDIV	JESD204C Reference Divider	Go
0x0109	MPY	JESD204C PLL Multiplier	Go
0x010A	RATE	JESD204C Receive Rate	Go
0x010B	LB_VRANGE	JESD204C VCO Range	Go
0x010C-0x011F	RESERVED
0x0120	JSYNC_N	JESD204C Manual Sync Request	Go
0x0121	JTEST	JESD204C Test Control	Go
0x0122-0x0123	RESERVED	RESERVED
0x0124	JTIMER	JESD204C Watchdog Timer	Go
0x0125-0x0126	RESERVED
0x0127	SYNC_EPW	JESD204C SYNC Error Report Pulse Width	Go
0x0128	CRC_TH	JESD204C CRC Error Thresholds	Go
0x0129-0x012B	RESERVED
0x012C	LANE_ARSTAT	Lane Arrival Status	Go
0x012D	RESERVED
0x012E-0x012F	LANE_INV	PHY Lane Inversion	Go
0x0130-0x013F	LANE_SEL[15:0]	PHY Lane Select for Logical Lane n	Go
0x0140-0x014F	LANE_ARR[15:0]	Lane n Arrival Time	Go
0x0150-0x015F	LANE_STATUS[15:0]	Lane n Status	Go
0x0160-0x016F	LANE_ERR[15:0]	Lane n Error Flags	Go
0x0170-0x017F	FIFO_STATUS[15:0]	Gearbox FIFO Status for Logical Lane n	Go
0x0180-0x0189	RESERVED
0x018A-0x019F	RESERVED
0x01A0	BER_EN	BER Measurement Control	Go
0x01A1-0x01AF	RESERVED
0x01B0-0x01BF	BER_CNT[15:0]	BER Error Count for Lane n	Go
0x01C0	RESERVED
0x01C1	JPHY_CTRL	SerDes PHY Control	Go
0x01C2	EQ_CTRL	SerDes Equalizer Control	Go
0x01C3	EQZERO	SerDes Equalizer Zero	Go
0x01D0-0x01DF	LANE_EQ[15:0]	SerDes Equalizer Level for Lane n	Go
0x01E0-0x01EF	LANE_EQS[15:0]	SerDes Equalizer Status for Lane n	Go
0x1F0	ESRUN	SerDes Eye-Scan Run Control	Go
0x01F1	ES_CTRL	SerDes Eye-Scan Control	Go
0x01F2	ESPO	SerDes Eye-Scan Phase Offset	Go
0x01F3	ESVO	SerDes Eye-Scan Voltage Offset	Go
0x01F4	ES_BIT_SELECT	SerDes Eye-Scan Bit Select	Go
0x01F5	ESCOUNT_CLR	SerDes Error Counter Clear	Go
0x01F6-0x01F7	ESDONE	SerDes Eye-Scan Process Done	Go
0x01F8-0x01FF	RESERVED
0x0200-0x020F	ESVO_S[15:0]	SerDes Eye-Scan Voltage Offset for Lane n	Go
0x0210-0x022F	ECOUNT[15:0]	SerDes Error/Mismatch Count for Lane n	Go
0x0230-0x0233	RESERVED
0x0234	LOS_TH	SerDes Loss-of_Signal Threshold	Go
0x0235	EQCNTSZ	SerDes Equalizer Counter Size	Go
0x0236-0x237	RESERVED
0x0238	CDRLOCK	SerDes CDR Lock/Freeze	Go
0x0239	CDRPHASE	SerDes CDR Phase Status	Go
0x023A-0x024F	RESERVED
0x0250	PLL_STATUS	SerDes PLL Status	Go
0x0251-0x0252	RESERVED
0x0253	JESD_RST	JESD Reset	Go
0x0254-0x02AF	RESERVED
0x02B0	EXTREF_EN	Enable External Reference	Go
0x02B1	CUR_2X_EN	DAC Current Doubler Enable	Go
0x02B2-0x02C1	RESERVED
0x02C2-0x02CE	RESERVED
0x02CF	DAC_OFS_CHG_BLK	DAC Offset Adjustment Change Block	Go
0x02D0-0x02DF	RESERVED
0x02E0	DP_EN	Datapath Enable	Go
0x02E1	DUC_L	DUC Interpolation Factor	Go
0x02E2	DUC_GAIN	DUC Gain	Go
0x02E3	DUC_FORMAT	DUC Output Format	Go
0x02E4	DAC_SRC	DAC Source	Go
0x02E5-0x02E7	RESERVED
0x02E8	MXMODE	DAC Output Mode	Go
0x02E9	RESERVED
0x02EA	TRUNC_HLSB	Truncation Half LSB Offset	Go
0x02EB-0x02F7	RESERVED
0x02F8	TX_EN_SEL	Transmitter Enable Control Selection	Go
0x02F9	TX_EN	Transmitter Enable Configuration	Go
0x02FA-0x02FF	RESERVED
0x0300	NCO_CTRL	NCO Control	Go
0x0301	NCO_CONT	NCO Phase Continuous Mode	Go
0x0302	NCO_SYNC	NCO Synchronization Configuration	Go
0x0303	NCO_AR	NCO Accumulator Reset	Go
0x0304	SPI_SYNC	SPI Sync	Go
0x0305	NCO_SS	NCO Continuous Self-Sync Mode	Go
0x0306-0x0317	RESERVED
0x0318-0x031F	AMP[3:0]	DDS Amplitude	Go
0x0320-0x0327	FREQ[0]	Frequency for NCO0 Accumulator	Go
0x0328-0x032F	FREQ[1]	Frequency for NCO1 Accumulator	Go
0x0330-0x0337	FREQ[2]	Frequency for NCO2 Accumulator	Go
0x0338-0x033F	FREQ[3]	Frequency for NCO3 Accumulator	Go
0x0340-0x0347	PHASE[3:0]	Phase for NCOn Accumulator	Go
0x0348-0x0377	RESERVED
0x0378-0x037F	AMP_R[3:0]	Readback for Amplitude Workd for NCOn	Go
0x0380-0x039F	FREQ_R[3:0]	Readback for Frequency for NCOn Accumulator	Go
0x03A0-0x03A7	PHASE_R[3:0]	Readback for Phase Word for NCOn Accumulator	Go
0x03A8-0x03DF	RESERVED
0x03E0	FR_FRS_R	Readback for FR Synchronization	Go
0x03E1	FR_NCO_AR_R	Readback for FR NCO Accumulator Reset	Go
0x03E2-0x03FF	RESERVED
0x0400	TS_TEMP	Tempeature Reading in Celsius	Go
0x0401	TS_SLEEP	Temperature Sensor Sleep	Go
0x0402-0x040F	RESERVED
0x0410	SYNC_STATUS	Synchronization Status	Go
0x0411-0x042F	RESERVED
0x0430	SYS_ALM	System Alarm Status	Go
0x0431	ALM_MASK	Alarm Mask	Go
0x0432	MUTE_MASK	DAC Mute Mask	Go
0x0433	MUTE_REC	DAC Mute Recovery	Go
0x0434-0x05FF	RESERVED
0x0600	FUSE_STATUS	Fuse Status	Go
0x0601-0x0722	RESERVED
0x0723	FINE_CUR_A	Fine Bias Current Control for DACA	Go
0x0724	COARSE_CUR_A	Coarse Bias Current Control for DACA	Go
0x0725	FINE_CUR_B	Fine Bias Current Control for DACB	Go
0x0726	COARSE_CUR_B	Coarse Bias Current Control for DACB	Go
0x0727	DEM_ADJ	DEM Adjust	Go
0x0728	RESERVED
0x0729	DEM_DITH	DEM and DITHER Control	Go
0x72A-0x072D	DAC_OFS	DAC_Offset_Adjustment	Go
0x72E - 0x7FF	RESERVED

7.5.3.1 CONFIG_A Register (Offset = 0h) [reset = 30h]

CONFIG_A is shown in Figure 7-61 and described in Table 7-33.

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Configuration A (default: 0x30)

Figure 7-61 CONFIG_A Register

7	6	5	4	3	2	1	0
SOFT_RESET	RESERVED	ASCEND	RESERVED	RESERVED
R/W-0h	R/W-0h	R/W-1h	R/W-1h	R/W-0h

Table 7-33 CONFIG_A Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SOFT_RESET	R/W	0h	Writing a 1 to this bit causes a full reset of the chip and all SPI registers (including CONFIG_A). This bit is self-clearing and will always read zero. After writing this bit, the part may take up to 5 ns to reset. During this time, do not perform any SPI transactions.
6	RESERVED	R/W	0h
5	ASCEND	R/W	1h	0 : Address is decremented during streaming reads/writes 1 : Address is incremented during streaming reads/writes (default)
4	RESERVED	R	1h	Always read 1.
3-0	RESERVED	R/W	0h

7.5.3.2 DEVICE_CONFIG Register (Offset = 2h) [reset = 00h]

DEVICE_CONFIG is shown in Figure 7-62 and described in Table 7-34.

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Device Configuration (default: 0x00)

Figure 7-62 DEVICE_CONFIG Register

7	6	5	4	3	2	1	0
RESERVED						MODE
R/W-0h						R/W-0h

Table 7-34 DEVICE_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R/W	0h
1-0	MODE	R/W	0h	0 : Normal operation (default) 1 : Reserved 2 : Reserved 3 : Full power down. The user should follow the recommendations in Section 8.1.6 in this mode to avoid reliability concerns.

Bit

Field

Type

Reset

Description

7-2

RESERVED

R/W

1-0

MODE

R/W

0 : Normal operation (default)

1 : Reserved

2 : Reserved

3 : Full power down. The user should follow the recommendations in Section 8.1.6 in this mode to avoid reliability concerns.

7.5.3.3 CHIP_TYPE Register (Offset = 3h) [reset = 04h]

CHIP_TYPE is shown in Figure 7-63 and described in Table 7-35.

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Chip Type (read-only: 0x04)

Figure 7-63 CHIP_TYPE Register

7	6	5	4	3	2	1	0
RESERVED				CHIP_TYPE
R/W-0h				R-4h

Table 7-35 CHIP_TYPE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0h
3-0	CHIP_TYPE	R	4h	Always returns 0x4, indicating that the part is a high speed DAC.

7.5.3.4 CHIP_ID Register (Offset = 4h) [reset = 003Bh]

CHIP_ID is shown in Figure 7-64 and described in Table 7-36.

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Chip Identification (read-only)

Figure 7-64 CHIP_ID Register

15	14	13	12	11	10	9	8
CHIP_ID
R-0h

7	6	5	4	3	2	1	0
CHIP_ID
R-3Bh

Table 7-36 CHIP_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	CHIP_ID	R	003Bh	Always returns 0x003B indicating it is the DAC39RF10 device family

7.5.3.5 CHIP_VERSION Register (Offset = 6h) [reset = 02h]

CHIP_VERSION is shown in Figure 7-65 and described in Table 7-37.

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Chip Version (read-only)

Figure 7-65 CHIP_VERSION Register

7	6	5	4	3	2	1	0
CHIP_VERSION
R-2h

Table 7-37 CHIP_VERSION Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CHIP_VERSION	R	02h	1: PG1.0 2: PG2.0

Bit

Field

Type

Reset

Description

7-0

CHIP_VERSION

02h

1: PG1.0

2: PG2.0

7.5.3.6 VENDOR_ID Register (Offset = Ch) [reset = 0451h]

VENDOR_ID is shown in Figure 7-66 and described in Table 7-38.

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Vendor Identification (default: 0x0451)

Figure 7-66 VENDOR_ID Register

15	14	13	12	11	10	9	8
VENDOR_ID
R-04h

7	6	5	4	3	2	1	0
VENDOR_ID
R-51h

Table 7-38 VENDOR_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	VENDOR_ID	R	451h	TI vendor ID

7.5.3.7 SYSREF_CTRL Register (Offset = 0080h) [reset = 40h]

SYSREF_CTRL is shown in Figure 7-67 and described in Table 7-39.

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SYSREF Control

Figure 7-67 SYSREF_CTRL Register

7	6	5	4	3	2	1	0
SYSREF_PROC_EN	SYSREF_RECV_SLEEP	SYSREF_PS_EN	SYSREF_ZOOM	SYSREF_SEL
R/W-0b	R/W-1b	R/W-0b	R/W-0b	R/W-0h

Table 7-39 SYSREF_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SYSREF_PROC_EN	R/W	0h	When set, this bit enables the SYSREF processor. When this is enabled, the system receives and processes each new SYSREF edge. User should always clear SYSREF_RECV_SLEEP before setting this bit. This bit is provided to allow the SYSREF receiver to stabilize before allowing the SYSREF to come to the digital.
6	SYSREF_RECV_SLEEP	R/W	1b	Clear this bit to enable the SYSREF receiver circuit. User should always clear SYSREF_PROC_EN before setting this bit.
5	SYSREF_PS_EN	R/W	0b	When set, SYSREF_POS will contain 1’s for all positions that have been detected as near the SYSREF edge since this bit was set. When cleared, SYSREF_POS will only contain 1’s for the last SYSREF edge that was detected.
4	SYSREF_ZOOM	R/W	0b	Set this bit to “zoom” in the SYSREF strobe status (impacts SYSREF_POS and the step size of SYSREF_SEL).
3-0	SYSREF_SEL	R/W	0b	Set this field to select which SYSREF delay to use. Set this based on the results returned by SYSREF_POS.

7.5.3.8 SYSREF_POS Register (Offset = 90h) [reset = NA]

SYSREF_POS is shown in Figure 7-68 and described in Table 7-40.

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SYSREF Position Capture

Figure 7-68 SYSREF_POS Register

23	22	21	20	19	18	17	16
RESERVED				SYSREF_POS
R				R
15	14	13	12	11	10	9	8
SYSREF_POS
R
7	6	5	4	3	2	1	0
SYSREF_POS
R

Table 7-40 SYSREF_POS Register Field Descriptions

Bit	Field	Type	Reset	Description
23-20	Reserved	R	0x0	Reserved
19-0	SYSREF_POS	R	NA	Returns a 20-bit status value that indicates the position of the SYSREF edge with respect to CLK. Use this to determine the proper programming for SYSREF_SEL, and SYSREF_ZOOM.

7.5.3.9 SYSREF_ALIGN Register (Offset = 00A0h) [reset = 00h]

SYSREF_ALIGN is shown in Figure 7-69 and described in Table 7-41.

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SYSREF Alignment Control

Figure 7-69 SYSREF_ALIGN Register

7	6	5	4	3	2	1	0
RESERVED							SYSREF_ALIGN_EN
R/W-00h							R/W-0b

Table 7-41 SYSREF_ALIGN Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h	Reserved
0	SYSREF_ALIGN_EN	R/W	0b	When this bit is set, the chip realigns to each detected SYSREF edge. This affects both the external clock divider and the JESD subsystem.

SYSREF_TERM Register (Offset = 00A1h) [reset = 00h]

SYSREF_TERM is shown in Figure 7-70 and described in Table 7-42.

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SYSREF Termination Configruation

Figure 7-70 SYSREF_TERM Register

7	6	5	4	3	2	1	0
RESERVED							SYSREF_RECV_LVPECL
R/W-00h							R/W-0b

Table 7-42 SYSREF_TERM Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

Reserved

SYSREF_RECV_LVPECL

R/W

0: SYSREF termination is 100 Ohm differential with Vcm of 0.4V

1: SYSREF termination is singled ended 50 Ohm to GND (LVPECL mode)

7.5.3.10 JESD_EN Register (Offset = 0100h) [reset = 00h]

JESD_EN is shown in Figure 7-71 and described in Table 7-43.

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JESD204C Subsystem Enable

Figure 7-71 JESD_EN Register

7	6	5	4	3	2	1	0
RESERVED							JESD_EN
R/W-00h							R/W-0b

Table 7-43 JESD_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

JESD_EN

R/W

0 : Disable JESD204C interface

1 : Enable JESD204C interface

When JESD_EN=0, the JESD204C subsystem is held in reset and the SERDES PHY is disabled. The LMFC/LEMC counter is also held in reset, so SYSREF will not align the LMFC/LEMC.

Note: This register should only be changed when DP_EN=0.

7.5.3.11 JMODE Register (Offset = 0101h) [reset = 00h]

JMODE is shown in Figure 7-72 and described in Table 7-44.

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JESD204C Mode

Figure 7-72 JMODE Register

7	6	5	4	3	2	1	0
RESERVED		JMODE
R/W-00b		R/W-000000b

Table 7-44 JMODE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

R/W

00b

5-0

JMODE

000000b

Specify the JESD204C interface mode. See Table 7-22.

Note: This register should only be changed when JESD_EN=0.

7.5.3.12 JESD_M Register (Offset = 0102h) [reset = 01h]

JESD_M is shown in Figure 7-73 and described in Table 7-45.

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JESD204C Number of Streams

Figure 7-73 JESD_M Register

7	6	5	4	3	2	1	0
				JESD_M
R/W-0h				R/W-1h

Table 7-45 JESD_M Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R/W

3-0

JESD_M

R/W

Specify the number of sample streams to enable (JESD204C M parameter). The supported settings for JESD_M depend on the DUC interpolation (DUC_L) and Mx.

L_DUC: Supported Settings for JESD_M

1x: 1 or 2 (but never larger than Mx)

2x or 3x: 2 (but never larger than Mx)

4x or 6x: 2 or 4 (but never larger than Mx)

8x or higher:2, 4, 6 or 8 (but never larger than Mx)

See Table 7-22 for the Mx value associated with each JMODE. The number of lanes enabled (L) is computed as: L=ceiling(M/Mx*Lx). An I/Q pair counts as two streams. For example, when inputting 4 IQ streams, program JESD_M=8.

Note: This register should only be changed when JESD_EN=0 and DP_EN=0.

7.5.3.13 JCTRL Register (Offset = 0103h) [reset = 03h]

JCTRL is shown in Figure 7-74 and described in Table 7-46.

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JESD204C Control. This register should only be changed when JESD_EN = 0.

Figure 7-74 JCTRL Register

7	6	5	4	3	2	1	0
RESERVED	TI_MODE	SUBCLASS	JENC	RESERVED		SFORMAT	SCR
R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-00b		R/W-1b	R/W-1b

Table 7-46 JCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0b
6	TI_MODE	R/W	0b	0 : JESD204C standard mode (default) 1 : TI Mode - set this when using TI FPGA transmitter IP
5	SUBCLASS	R/W	0b	Specify how the elastic buffer is released: 0 : Subclass 0 operation (default). Release the elastic buffer immediately once all lanes have starting writing to the buffer. 1 : Subclass 1 operation. Release the elastic buffer on a release opportunity defined by the LMFC/LEMC and RBD.
4	JENC	R/W	0b	0 : Use 8b/10b link layer 1 : Use 64b/66b link layer
3-2	RESERVED	R/W	0b
1	SFORMAT	R/W	1b	Input sample format for JESD204C samples 0 : Offset binary 1 : Signed 2’s complement (default)
0	SCR	R/W	1b	0 : 8b/10b Scrambler disabled 1 : 8b/10b Scrambler enabled (default) The 8b/10b scrambler is recommended to improve spurious noise and make sure that certain sample payloads cannot prevent the JESD204C receiver from detecting incorrect code-group or lane alignment. This register has no effect on 64b/66b modes (which are always scrambled).

7.5.3.14 SHMODE Register (Offset = 0104h) [reset = 00h]

SHMODE is shown in Figure 7-75 and described in Table 7-47.

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JESD204C Sync Word Mode

Figure 7-75 SHMODE Register

7	6	5	4	3	2	1	0
RESERVED						SHMODE
R/W-0b						R/W-00b

Table 7-47 SHMODE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

RESERVED

R/W

00h

1-0

SHMODE

R/W

00b

Select the mode for the 64b/66b sync word (32 bits of data per multi-block). This only applies when JENC=1 (64b/66b mode).

0 : Enable CRC-12 checking (JESD204C Table 41) (default setting)

1 : RESERVED

2 : RESERVED

3 : RESERVED

Note: This device does not support any JESD204C command features. All command fields are ignored by the receiver.

Note: This register should only be changed when JESD_EN=0.

7.5.3.15 KM1 Register (Offset = 0105h) [reset = 1Fh]

KM1 is shown in Figure 7-76 and described in Table 7-48.

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JESD204C K Parameter (minus 1)

Figure 7-76 KM1 Register

7	6	5	4	3	2	1	0
KM1
R/W-1Fh

Table 7-48 KM1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	KM1	R/W	1Fh	K is the number of frames per multiframe, and K-1 shall be programmed here when using the 8b/10b link layer (see JENC). Depending on the JMODE setting, there are constraints on the legal values of K (see Table 7-22 and KR). Programming an illegal value for K will cause the link to malfunction. The default value is KM1=31, which corresponds to K=32. Note: For modes using the 64b/66b link layer, the KM1 register is ignored. The effective value of K is 256*E/F. Note: This register should only be changed when JESD_EN=0.

Bit

Field

Type

Reset

Description

7-0

KM1

R/W

1Fh

K is the number of frames per multiframe, and K-1 shall be programmed here when using the 8b/10b link layer (see JENC). Depending on the JMODE setting, there are constraints on the legal values of K (see Table 7-22 and KR). Programming an illegal value for K will cause the link to malfunction.

The default value is KM1=31, which corresponds to K=32.

Note: For modes using the 64b/66b link layer, the KM1 register is ignored. The effective value of K is 256*E/F.

Note: This register should only be changed when JESD_EN=0.

7.5.3.16 RBD Register (Offset = 106h) [reset = 00h]

RBD is shown in Figure 7-77 and described in Table 7-49.

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JESD204C Release Buffer Delay

Figure 7-77 RBD Register

7	6	5	4	3	2	1	0
RESERVED		RBD
R/W-0b		R/W-000000b

Table 7-49 RBD Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

R/W

00b

5-0

RBD

R/W

000000b

This register shifts the elastic buffer release opportunities. Increasing RBD by 1 delays the release opportunities by 4 bytes (octets).

The legal RBD range is 0 to K*F/4-1.

For 64b/66b modes, the legal RBD range is 0 to 63.

See Programming RBD.

Note: This register should only be changed when JESD_EN=0.

7.5.3.17 JESD_STATUS Register (Offset = 0107h) [reset = NA]

JESD_STATUS is shown in Figure 7-78 and described in Table 7-50.

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JESD204C / System Status

Figure 7-78 JESD_STATUS Register

7	6	5	4	3	2	1	0
EB_ERR	LINK_UP	JSYNC_STATE	REALIGNED	ALIGNED	PLL_LOCKED	RESERVED
R/W1C	R	R	R/W1C	R	R	R

Table 7-50 JESD_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EB_ERR	R/W1C	NA	Elastic buffer experienced underflow/overflow. Check RBD. Write a 1 to clear this bit.
6	LINK_UP	R	NA	When set, indicates that the JESD204C link is up (elastic buffer released).
5	JSYNC_STATE	R	NA	Returns the state of the JESD204C SYNC signal. 0 : SYNC asserted 1 : SYNC de-asserted
4	REALIGNED	R/W1C	NA	When any clock dividers or the LMFC/LEMC counters are realigned by SYSREF, this bit gets set. Write a 1 to clear this bit. The behavior of this bit is undefined when SUBCLASS=0.
3	ALIGNED	R	NA	When set, indicates that the last SYSREF pulse was consistent with the SYSREF-associated clock dividers (including the LMFC/LEMC). This bit is read-only (cannot be cleared via SPI). After JESD_EN is set, the part may require up to 7 SYSREF pulses to achieve full alignment and set this bit. The behavior of this bit is undefined when SUBCLASS=0.
2	PLL_LOCKED	R	NA	When high, indicates that all enabled SerDes PLLs are locked.
1-0	RESERVED	R	NA

7.5.3.18 REFDIV Register (Offset = 0108h) [reset = 30h]

REFDIV is shown in Figure 7-79 and described in Table 7-51.

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JESD204C Reference Divider

Figure 7-79 REFDIV Register

7	6	5	4	3	2	1	0
RESERVED		REFDIV
R/W-0b		R/W-30h

Table 7-51 REFDIV Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

R/W

00b

5-0

REFDIV

R/W

30h

Specifies the frequency divisor to generate the PHY PLL reference clock (FREF) from the DAC clock (F_CLK). See PLL Control.

The following values are legal: 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40, 48. All other values are reserved and produce undefined behavior.

7.5.3.19 MPY Register (Offset = 0109h) [reset = 14h]

MPY is shown in Figure 7-80 and described in Table 7-52.

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JESD204C PLL Multiplier

Figure 7-80 MPY Register

7	6	5	4	3	2	1	0
MPY
R/W-14h

Table 7-52 MPY Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	MPY	R/W	14h	Specifies the PLL frequency multiplier for the PHY. See PLL Control. The following values are allowed for this design: MPY: Frequency Multiplier 16 (0x10): 4 20 (0x14): 5 33 (0x21): 8.25 40 (0x28): 10 Note: This register should only be changed when JESD_EN=0.

Bit

Field

Type

Reset

Description

7-0

MPY

R/W

14h

Specifies the PLL frequency multiplier for the PHY. See PLL Control. The following values are allowed for this design:

MPY: Frequency Multiplier

16 (0x10): 4

20 (0x14): 5

33 (0x21): 8.25

40 (0x28): 10

Note: This register should only be changed when JESD_EN=0.

7.5.3.20 RATE Register (Offset = 010Ah) [reset = 00h]

RATE is shown in Figure 7-81 and described in Table 7-53.

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JESD204C Receive Rate

Figure 7-81 RATE Register

7	6	5	4	3	2	1	0
RESERVED						RATE
R/W-00h						R/W-00b

Table 7-53 RATE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

RESERVED

R/W

00h

1-0

RATE

R/W

00b

Controls the frequency multiplier from the PHY PLL to the serial line rate. See PLL Control. Affects all lanes.

RATE: Multiplier

00b: 4

01b: 2

10b: 1

11b: 0.5

Note: This register should only be changed when JESD_EN=0.

7.5.3.21 LB_VRANGE Register (Offset = 010Bh) [reset = 00h]

LB_VRANGE is shown in Figure 7-82 and described in Table 7-54.

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JESD204C PLL VCO Range. Note: This register should only be changed when JESD_EN=0.

Figure 7-82 LB_VRANGE Register

7	6	5	4	3	2	1	0
RESERVED							VRANGE
R/W-0h							R/W-0b

Table 7-54 LB_VRANGE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h
0	VRANGE	R/W	0b	This bit must be set if the PLL/VCO frequency is below 2.17GHz. See PLL Control.

7.5.3.22 JSYNC_N Register (Offset = 0120h) [reset = 01h]

JSYNC_N is shown in Figure 7-67 and described in Table 7-39.

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JESD204C Manual Sync Request

Figure 7-83 JSYNC_N Register

7	6	5	4	3	2	1	0
RESERVED							JSYNC_N
R/W-00h							R/W1C

Table 7-55 JSYNC_N Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

JSYNC_N

R/W

Set this bit to 0 to manually assert the SYNC signal. For normal operation, leave this bit set to 1.

Note: Behavior of JSYNC_N=0 is undefined when JENC=1.

7.5.3.23 JTEST Register (Offset = 0121h) [reset = 00h]

JTEST is shown in Figure 7-84 and described in Table 7-56.

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JESD204C Test Control

Figure 7-84 JTEST Register

7	6	5	4	3	2	1	0
RESERVED			JTEST
R/W-000b			R/W-00h

Table 7-56 JTEST Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	0h
4-0	JTEST	R/W	0b	PRBS Test Modes: 0 : Test mode disabled. Normal operation (default) 1 : PRBS7 test mode 2 : PRBS9 test mode 3 : PRBS15 test mode 4 : PRBS31 test mode 5-31: RESERVED When a PRBS test mode is enabled, see BER_EN. Note: This register should only be changed when JESD_EN=0.

Bit

Field

Type

Reset

Description

7-5

RESERVED

R/W

4-0

JTEST

R/W

PRBS Test Modes:

0 : Test mode disabled. Normal operation (default)

1 : PRBS7 test mode

2 : PRBS9 test mode

3 : PRBS15 test mode

4 : PRBS31 test mode

5-31: RESERVED

When a PRBS test mode is enabled, see BER_EN.

Note: This register should only be changed when JESD_EN=0.

7.5.3.24 JTIMER Register (Offset = 0124h) [reset = 00h]

JTIMER is shown in Figure 7-85 and described in Table 7-57.

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Note: This register should only be changed when JESD_EN=0.

JESD204C Watchdog Timer

Figure 7-85 JTIMER Register

7	6	5	4	3	2	1	0
JTPLL	RESERVED	JTR		RESERVED	JTT
R/W-0b	R/W-0b	R/W-0b		R/W-0b	R/W-000b

Table 7-57 JTIMER Register Field Descriptions

Bit	Field	Type	Reset	Description
7	JTPLL	R/W	1b	When this bit is set, the SerDes PLL is also reset when the watchdog timer expires. When this bit is 0, only the SerDes receiver is reset.
6	RESERVED	R/W	0b
5-4	JTR	R/W	00b	This register determines how much the watchdog counter is decremented when the link is up and CRC_FAULT is not set. JTR : Watchdog Counter Decrement : Approximate Link Uptime % required to prevent the SerDes from being reset 0 : 1 : 99.25% 1 : 2 : 98.46% 2 : 8 : 94.12% 3 : 16 : 88.89%
3	RESERVED	R/W	0b
2-0	JTT	R/W	0b	JESD204C watchdog counter threshold. When the watchdog counter reaches the threshold defined by JTT, the PHY layer is reset (including the PHY PLL(s) if JTPLL=1) and the watchdog timer is reset. Larger values of JTT cause the watchdog timer to take longer to intervene. JTT : Watchdog Counter Threshold : Counter Duration [assuming F_CLK = 10.24 GHz 0 : <Watchdog Timer Disabled> : <disabled> 1 : 2¹⁷ : 102.4 μs 2 : 2¹⁹ : 409.6 μs 3 : 2³² : 1.63 ms 4 : 2²³ : 6.55 ms 5-7 : RESERVED : RESERVED Note: The watchdog may not detect link up events shorter than 2¹⁰ (1024) CLK cycles.

7.5.3.25 SYNC_EPW Register (Offset = 0127h) [reset = 00h]

SYNC_EPW is shown in Figure 7-86 and described in Table 7-58.

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JESD204C SYNC Error Report Pulse Width

Figure 7-86 SYNC_EPW Register

7	6	5	4	3	2	1	0
RESERVED					SYNC_EPW
R/W-00h					R/W-000b

Table 7-58 SYNC_EPW Register Field Descriptions

Bit

Field

Type

Reset

Description

7-3

RESERVED

R/W

00h

2-0

SYNC_EPW

R/W

000b

Specifies the pulse width of SYNC that is used for reporting errors to the transmitter. When an error is detected that does not require link resynchronization, SYNC is asserted for SYNC_EPW link clock cycles (equal to 4*SYNC_EPW character durations). To disable error reporting over SYNC, set SYNC_EPW=0. The legal range for SYNC_EPW is 0 to 7.

Note: This register should only be changed when JESD_EN= 0.

7.5.3.26 CRC_TH Register (Offset = 0128h) [reset = 00h]

CRC_TH is shown in Figure 7-87 and described in Table 7-59.

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JESD204C CRC Error Thresholds

Figure 7-87 CRC_TH Register

7	6	5	4	3	2	1	0
RESERVED				CRC_ERR_REC		CFC_ERR_TH
R/W-0h				R/W-00b		R/W-00b

Table 7-59 CRC_TH Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0h
3-2	CRC_ERR_REC	R/W	0b	Specify how many contiguous, error-free multiblocks must be received to reset the CRC error counter (and un-trigger the CRC alarm if triggered). 0 : 1 multiblock 1 : 4 multiblocks 2 : 16 multiblocks 3 : 64 multiblocks
1-0	CRC_ERR_TH	R/W	0b	Specify how many multi-blocks must have CRC errors to trigger the CRC alarm. The receiver counts each error, but if a run of error-free multi-blocks occurs (as specified by CRC_ERR_REC), the error counter resets. 0 : 1 multiblock 1 : 2 multiblocks 2 : 4 multiblocks 3 : 8 multiblocks
Note: For each lane, the internal signal, CRC_FAULT, is set if the number of multi-blocks with CRC errors exceeds the threshold set by CRC_ERR_TH without a run of contiguous, error-free multi-blocks specified by CRC_ERR_REC. CRC_FAULT is cleared when a run of contiguous, error-free multi-blocks specified by CRC_ERR_REC is detected. Note: This register should only be changed when JESD_EN=0.

7.5.3.27 LANE_ARSTAT Register (Offset = 012Ch) [reset = NA]

LANE_ARSTAT is shown in Figure 7-88 and described in Table 7-60.

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Lane Arrival Status

Figure 7-88 LANE_ARSTAT Register

7	6	5	4	3	2	1	0
RESERVED							LANE_ARR_RDY
R/W-00h							R

Table 7-60 LANE_ARSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h
0	LANE_ARR_RDY	R	NA	This bit is set when lane arrival times are captured and available for read in LANE_ARR. Lane arrival data is captured when all lanes are ready and the chip attempts to release the elastic buffer. This bit is cleared when JESD_EN=0 or JESD_RST=1.

7.5.3.28 LANE_INV Register (Offset = 012Eh) [reset = 0000h]

LANE_INV is shown in Figure 7-89 and described in Table 7-61.

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SerDes Lane Inversion

Note: Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-89 LANE_INV Register

15	14	13	12	11	10	9	8
LANE_INV[15:8]
R/W-00h
7	6	5	4	3	2	1	0
LANE_INV[7:0]
R/W-00h

Table 7-61 LANE_INV Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	LANE_INV	R/W	0000h	Program LANE_INV[n]=1 to invert the bitstream through physical lane n. Use this if the differential pair is swapped between the transmitter and receiver.

7.5.3.29 LANE_SEL[15:0] Register (Offset = 0130h) [reset for LANE_SEL[n]=n]

LANE_SEL[15:0] forms a crossbar switch, and is a set of 16 registers for specifying which physical lane is bound to logical lane n. LANE_SEL[15:0] is shown in Figure 7-90 and described in Table 7-62.

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SerDes Lane Select for Logical Lane n (n = 0 - 15). LANE_SEL[0] is at the lowest address.

Note: Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-90 LANE_SEL[15:0] Register

7	6	5	4	3	2	1	0
RESERVED				LANE_SEL[n]
R/W-0h				R/W-n

Table 7-62 LANE_SEL[15:0] Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R/W

3-0

LANE_SEL[n]

R/W

Specify which physical lane (0 to 15) is bound to logical lane n. To bind physical lane p to logical lane n, program LANE_SEL[n]=p. For example, to bind logical lane 0 to physical lane 3, program LANE_SEL[0]=3.

Note: This register should only be changed when JESD_EN=0.

7.5.3.30 LANE_ARR[15:0] Register (Offset = 0140h) [Read only, reset = NA]

LANE_ARR[15:0] is a set of 16 registers for measuring the arrival time of lane n. LANE_ARR[15:0] is shown in Figure 7-91 and described in Table 7-63.

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SerDes Lane n Arrival Time (n = 0 - 15). LANE_ARR[0] is at the lowest address.

Note: Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-91 LANE_ARR[15:0] Register

7	6	5	4	3	2	1	0
RESERVED		LANE_ARR[n]
R-00b		R

Table 7-63 LANE_ARR[15:0] Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

5-0

LANE_ARR[n]

Returns the arrival time of lane n with respect to the internal LMFC/LEMC that is established by SYSREF. The value returned can be between 0 and 63 (inclusive), regardless of the multiframe/EMB length. These registers are valid only when LANE_ARR_RDY =1. See Programming RBD.

Note: The lane arrival data is captured when attempting to release the elastic buffer and LANE_ARR_RDY=0. All values are from the same release attempt.

Note: It may be necessary to use JESD_RST when starting the link to get accurate lane arrival values.

7.5.3.31 LANE_STATUS[15:0] Register (Offset = 0150h) [Read only, reset = NA]

LANE_STATUS[15:0] is a set of 16 registers showing the status of lane n. LANE_STATUS[15:0] is shown in Figure 7-92 and described in Table 7-64.

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SerDes Lane n Status (n = 0 - 15). LANE_STATUS[0] is at the lowest address.

Note: Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-92 LANE_STATUS[15:0] Register

7	6	5	4	3	2	1	0
RESERVED					LANE_STATUS[n]
R-00h					R

Table 7-64 LANE_STATUS[15:0] Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R	00h
2	F_EMB_SYNC[n]	R	NA	Returns 1 if logical lane n has frame or EMB synchronization.
1	CG_BK_SYNC[n]	R	NA	Returns 1 if logical lane n has code-group or block synchronization.
0	SIG_DET[n]	R	NA	Returns 1 if logical lane n is detecting a data signal (using loss-of-signal detector in PHY).

7.5.3.32 LANE_ERR[15:0] Register (Offset = 0160h) [reset = 00h]

LANE_ERR[15:0] is a set of 16 registers reporting errors for lane n. LANE_ERR[15:0] is shown in Figure 7-93 and described in Table 7-65.

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SerDes Lane n Error Flags (n = 0 - 15). LANE_ERR[0] is at the lowest address.

Note: Only lanes 6 and 14 are connected on DDS devices. All other langes are disconnected.

Figure 7-93 LANE_ERR[15:0] Register

7	6	5	4	3	2	1	0
LANE_ERR[n]
R/W1C

Table 7-65 LANE_ERR[15:0] Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

LANE_ERR[n]

R/W1C

00h

Sticky bits indicating various errors on lane n. A bit is set to indicate an error. Write a 1 to clear a bit.

[7] Alignment character found at unexpected location (8b/10b) or (extended)-multi-block pilot signal not in expected location (64b/66b)

[6] Multi-frame, multi-block, or extended-multi-block alignment lost.

[5] Frame alignment was lost (8b/10b only) or CRC_FAULT=1 (64b/66b).

[4] Code-group or block synchronization was lost.

[3] RESERVED

[2] Not-in-table or unexpected control character (8b/10b) or CRC (64b/66b) error occurred.

[1] Disparity error (8b/10b) or invalid sync header (64b/66b) occurred.

[0] Gearbox FIFO overflowed or underflowed. As long as the write clock frequency is correct the gearbox write clock can drift at least 3UI after this flag without causing data corruption.

Note: Lane Error Flags for extra or disabled lanes are undefined.

Note: LANE_ERR[6:1] are only detected for 8b/10b operation while sync_n=1

7.5.3.33 FIFO_STATUS[15:0] Register (Offset = 0170h) [Read only, reset = NA]

FIFO_STATUS[15:0] is a set of 16 registers showing the status of lane n. LANE_STATUS[15:0] is shown in Figure 7-94 and described in Table 7-66.

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SerDes Lane n Status (n = 0 - 15). FIFO_STATUS[0] is at the lowest address.

Note: Only lanes 6 and 14 are connected on DDS devices. All other langes are disconnected.

Figure 7-94 FIFO_STATUS[15:0] Register

7	6	5	4	3	2	1	0
RESERVED			PDIFF[n]
R-000b			R

Table 7-66 FIFO_STATUS[15:0] Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

RESERVED

000b

4-0

PDIFF[n]

This register returns the difference between the write and read pointers inside the gearbox FIFO for logical lane n.

For 8b/10b, values from 0-14 will be returned. For 64b/66b, values from 0-16 will be returned.

The values at the ends of the range (0 & 14 for 8b/10b or 0 & 16 for 64b/66b) indicate error positions that will cause the Gearbox FIFO overflow/underflow flag to be set in LANE_ERR. In both cases, 1 indicates minimum setup and the max value minus 1 indicates minimum hold.

Values are measured in the read clock. The tread size is approximately ½ of the effective link layer clock period (0.5/(LCR*FDR)). In terms of UI:

In 8b/10b mode, the nominal tread size is 20UI. The nominal tread size for the final tread (14) is 380UI±20UI.
In 64b/66b mode, the nominal tread size is 16.5UI. The nominal tread size for the final tread (16) is 412.5UI±16.5UI.

The PDIFF[n] value for disabled lanes and lanes enabled by EXTRA_LANE are undefined.

7.5.3.34 BER_EN Register (Offset = 01A0h) [reset = 00h]

BER_EN is shown in Figure 7-95 and described in Table 7-67.

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BER Measurement Control

Figure 7-95 BER_EN Register

7	6	5	4	3	2	1	0
RESERVED							BER_EN
R/W-0b							R/W-0b

Table 7-67 BER_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h
0	BER_EN	R/W	0b	BER (bit-error-rate) test enable. After setting up the receiver parameters, the user can program JTEST to a PRBS mode, set JESD_EN, and then set BER_EN to enable the BER counters (see BER_CNTn). To clear and restart the counters, program BER_EN to 0 and then back to 1. The BER logic will self-synchronize to the incoming PRBS data after the rising edge of BER_EN.

7.5.3.35 BER_CNT Register (Offset = 01B0h) [reset = NA, read rnly]

BER_CNT is shown in Figure 7-96 and described in Table 7-68.

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BER Error Count for Lane n. Lane 0 is a the lowest address

Figure 7-96 BER_CNT Register

7	6	5	4	3	2	1	0
BER_CNT[n]
R/W-0b

Table 7-68 BER_CNT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

BER_CNT[n]

R/W

Returns the number of bit errors detected on lane n. This value will saturate at 255. The BER for lane n can be computed as follows:

BER = BER_CNT[n] / FBIT / TBER

Where TBER is the number of seconds that has elapsed from when BER_EN was set to when BER_CNT[n] was read. TBER is measured by the host system or clock.

Example: If BER_CNT[n] returns 2, and FBIT is 12.8Gbps, and TBER is 3600 seconds, the bit-error-rate is 2/12.8e9/3600 = 43e-15

Note: The error counters on disabled lanes and lanes enabled by EXTRA_LANE are undefined.

7.5.3.36 JPHY_CTRL Register (Offset = 01C1h) [reset = 43h]

JPHY_CTRL is shown in Figure 7-97 and described in Table 7-69.

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JESD204C SerDes Control. Note: This register should only be changed when JESD_EN = 0.

Figure 7-97 JPHY_CTRL Register

7	6	5	4	3	2	1	0
RESERVED	CDR			RESERVED		OC_EN	LOS_EN
R/W-0b	R/W-100b			R/W-0b		R/W-1b	R/W-1b

Table 7-69 JPHY_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0b
6-4	CDR	R/W	100b	Control CDR (clock-data-recovery) setting. The default value should be appropriate, but other settings can be used to adjust the tracking rate or reduce CDR power consumption. The 2nd order modes are for tracking a frequency offset when the Tx and Rx do not share a common reference clock. This is not applicable to JESD204C. See CDR Settings.
3-2	RESERVED	R/W	00b
1	OC_EN	R/W	1b	Enable offset compensation/calibration for all lanes.
0	LOS_EN	R/W	1b	Enable loss-of-signal detector for all lanes.

Table 7-70 CDR Settings

CDR	Vote Threshold	Tracking Rate [ppm]	Order	Settling Time [UI]	Activity %
0	15	313	2^nd	36	83
1	7	607	2^nd	36	70
2	3	723	2^nd	36	50
3	1	868	2^nd	36	25
4 (default)	15	96	1^st	36	83
5	3	289	1^st	36	50
6	1	434	1^st	36	25
7	7	13	1^st	1524	5

7.5.3.37 EQ_CTRL Register (Offset = 01C2h) [reset = 00h]

EQ_CTRL is shown in Figure 7-98 and described in Table 7-71.

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SerDes Equalizer Control

Figure 7-98 EQ_CTRL Register

7	6	5	4	3	2	1	0
RESERVED			EQ_OVR	EQZ_OVR	EQHLD	EQMODE
R/W-000b			R/W-0b	R/W-0b	R/W-0b	R/W-00b

Table 7-71 EQ_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000b
4	EQ_OVR	R/W	0b	When EQMODE=1, you can program EQ_OVR=1 to over-ride the equalizer level using the EQLEVEL[n] registers. Affects all lanes.
3	EQZ_OVR	R/W	0b	Set this bit to enable the EQZERO register (to override the equalizer’s zero frequency). When EQZ_OVR=0, the frequency is set based on the RATE register. Affects all lanes.
2	EQHLD	R/W	0b	When the equalizer is in fully-adaptive mode (EQMODE=1 and EQ_OVR=0), programming EQHLD will freeze (hold) the adaptation loop (for all lanes).
1-0	EQMODE	R/W	00b	Sets the equalizer mode (for all lanes): See Equalizer. 0: Equalizer disabled. Flat response with maximum gain. 1: Equalizer enabled. The equalizer is fully adaptive if EQ_OVR=0. 2: Precursor equalization analysis. 3: Postcursor equalization analysis.

7.5.3.38 EQZERO Register (Offset = 01C3h) [reset = 00h]

EQZERO is shown in Figure 7-99 and described in Table 7-72.

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SerDes Equalizer Zero.

Figure 7-99 EQZERO Register

7	6	5	4	3	2	1	0
RESERVED			EQZERO
R/W-000b			R/W-00h

Table 7-72 EQZERO Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

RESERVED

R/W

000b

4-0

EQZERO

R/W

00h

When EQZ_OVR=1, this field over-rides the equalizer’s zero frequency (for all lanes). When EQZ_OVR=0, the zero frequency is set automatically based on the RATE setting.

0x1F: 365 MHz (default setting for full and half-rate, RATE = 0 or 1)

0x1E: 275 MHz

0x1D: 195 MHz

0x1B: 140 MHz (default setting for quarter-rate mode, RATE = 2)

0x19: 105 MHz

0x10: 75 MHz

0x08: 55 MHz (default setting for eighth-rate, RATE = 3)

0x00: 50 MHz

7.5.3.39 LANE_EQ[15:0] Register (Offset = 01D0h) [reset = 08h]

LANE_EQ[15:0] is shown in Figure 7-100 and described in Table 7-73.

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SerDes Equalizer Level for Physical Lane [n]. LANE_EQ[0] is at the lowest address.

Note: Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-100 LANE_EQ[15:0] Register

7	6	5	4	3	2	1	0
RESERVED	EQBOOST[n]		EQLEVEL[n]
R/W-0b	R/W-00b		R/W-00h

Table 7-73 LANE_EQ[15:0] Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

R/W

6-5

EQBOOST[n]

R/W

00b

Controls EQ boost for physical lane n.

EQBOOST : GAIN Boost : BW Change : Power Increase

0 : 0dB : 0% : 0mW

1 : 2dB : -30% : 0mW

2 : 4dB : +10% : 5mW

3 : 6dB : -20% : 5mW

4-0

EQLEVEL[n]

R/W

00h

When EQ_OVR=1, this field controls the equalization level for lane n. The valid range is from 0 (least equalization) to 16 (most equalization).

7.5.3.40 LANE_EQS[15:0] Register (Offset = 01E0h) [reset = NA, read only]

LANE_EQS[15:0] is shown in Figure 7-101 and described in Table 7-74.

Return to the Register Summary Table.

Serdes Equalizer Status for Physical Lane n

Note: Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-101 LANE_EQS[15:0] Register

7	6	5	4	3	2	1	0
RESERVED	EQOVER[n]	EQUNDER[n]	EQLEVEL_S[n]
R	R	R	R

Table 7-74 LANE_EQS[15:0] Register Field Descriptions

Bit	Field	Type	Description
7	RESERVED	R
6	EQOVER[n]	R	EQOVER status for PHY lane n pre/post cursor analysis. See Pre/Post Cursor Analysis Procedure.
5	EQUNDER[n]	R	EQUNDER status for PHY lane n pre/post cursor analysis. See Pre/Post Cursor Analysis Procedure..
4	EQLEVEL_S[n]	R	This field returns the equalizer level currently in effect for lane n. This is the count of the number of bits set in the thermometer encoded value from the stsrx EQLEVEL_S field for lane n.

7.5.3.41 ESRUN Register (Offset = 01F0h) [reset = 00h]

ESRUN is shown in Figure 7-102 and described in Table 7-75.

Return to the Register Summary Table.

Eye-Scan Run Control

Figure 7-102 ESRUN Register

7	6	5	4	3	2	1	0
RESERVED							ESRUN
R/W-00h							R/W-0b

Table 7-75 ESRUN Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h
0	ESRUN	R/W	0b	After setting up eye-scan, set ESRUN=1 to run the eye-scan test. See Eye Scan Procedure.

7.5.3.42 ES_CTRL Register (Offset = 01F1h) [reset = 00h]

ES_CTRL is shown in Figure 7-103 and described in Table 7-76.

Return to the Register Summary Table. Note: Only change this register while ESRUN=0.

Eye-Scan Control

Figure 7-103 ES_CTRL Register

7	6	5	4	3	2	1	0
RESERVED		ESLEN		ES
R/W-00b		R/W-00b		R/W-0h

Table 7-76 ES_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

ES_CTRL

R/W

00b

5-4

ESLEN

R/W

00b

Specify the length of the eye-scan test. Larger values will give more consistent results, but will take longer.

ESLEN : Number of Samples Analyzed

0 : 127

1 : 1032

2 : 8191

3 : 65535

Note: Many eye-scan modes only analyze zeros (or ones). Since they don’t analyze every sample, those modes will take longer to complete compared to a mode that analyzes all samples.

3-0

R/W

Specify the eye-scan mode. Applies to all lanes.

ES : Eye-Scan Mode

0 : Eye-scan disabled (default)

1 : Compare. Counts mismatches between the normal sampler and the eye-scan sampler. Analyzes zeros and ones.

2 : Compare zeros. Same as ES=1, but only analyzes zeros.

3 : Compare ones. Same as ES=1, but only analyzes ones.

4 : Count ones. Increments ECOUNTn when the eye-scan sample is 1.

5-7 : RESERVED

8 : Average zero. Adjusts ESVO_Sn to the average voltage for a zero.

9 : Outer zero. Adjusts ESVO_Sn to the lowest voltage for a zero.

10 : Inner zero. Adjusts ESVO_Sn to the highest voltage for a zero.

11 : RESERVED

12 : Average one. Adjusts ESVO_Sn to the average voltage for a one.

13 : Outer one. Adjusts ESVO_Sn to the highest voltage for a one.

14 : Inner one. Adjusts ESVO_Sn to the lowest voltage for a one.

15 : RESERVED

7.5.3.43 ESPO Register (Offset = 01F2h) [reset = 00h]

ESPO is shown in Figure 7-104 and described in Table 7-77.

Return to the Register Summary Table.

Eye-Scan Phase Offset

Figure 7-104 ESPO Register

7	6	5	4	3	2	1	0
RESERVED	ESPO
R/W-0b	R/W-00h

Table 7-77 ESPO Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

R/W

6-0

ESPO

R/W

Eye-scan phase offset for all lanes. This adjusts the sampling instant of the eye-scan sampler compared to the normal sampler. This is a signed value from -64 to +63 and the step size is 1/32th of a UI.

Note: Only change this register while ESRUN=0.

7.5.3.44 ESVO Register (Offset = 01F3h) [reset = 00h]

ESVO is shown in Figure 7-105 and described in Table 7-78.

Return to the Register Summary Table.

Eye-Scan Voltage Offset

Figure 7-105 ESVO Register

7	6	5	4	3	2	1	0
RESERVED		ESVO
R/W-00b		R/W-00h

Table 7-78 ESVO Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

RESERVED

R/W

5-0

ESVO

R/W

00h

Eye-scan voltage offset for all lanes. This adjusts the voltage threshold of the eye-scan sampler. This is a signed value from -32 to +31. The step size is about 10mV (giving an adjustment range of about -320mV to +310mV). This field is ignored for eye-scan modes that adjust the voltage offset automatically and return a result on ESVO_S[n].

Note: This register should only be changed when ESRUN=0.

7.5.3.45 ES_BIT_SELECT Register (Offset = 01F4h) [reset = 00h]

ES_BIT_SELECT is shown in Figure 7-106 and described in Table 7-79.

Return to the Register Summary Table.

Eye-Scan Bit Select.

Figure 7-106 ES_BIT_SELECT Register

7	6	5	4	3	2	1	0
RESERVED			ES_BIT_SELECT
R/W-000b			R/W-00h

Table 7-79 ES_BIT_SELECT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

RESERVED

R/W

000b

4-0

ES_BIT_SELECT

R/W

00h

Eye-scan only runs on every 20th bit. This field specifies which bit position the eye-scan runs on (valid range is 0 to 19). Eye-scans may be run with all possible values of ES_BIT_SELECT and the results combined. Alternatively, results can be kept separate to see the effects of any duty cycle distortion / repetitive jitter.

Note: This register should only be changed when ESRUN=0.

7.5.3.46 ECOUNT_CLR Register (Offset = 01F5h) [reset = 00h]

ECOUNT_CLR is shown in Figure 7-107 and described in Table 7-80.

Return to the Register Summary Table.

SerDes Error Counter Clear

Figure 7-107 ECOUNT_CLR Register

7	6	5	4	3	2	1	0
RESERVED							ECOUNT_CLR
R/W-00h							R/W-0b

Table 7-80 ECOUNT_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h
0	ECOUNT_CLR	R/W	0b	Program this to a 1 and then to 0 to clear the ECOUNT counters

7.5.3.47 ESDONE Register (Offset = 01F6h) [reset = NA, read-only]

ESDONE is shown in Figure 7-108 and described in Table 7-81.

Return to the Register Summary Table.

Eye-Scan Process Done

Note: Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-108 ESDONE Register

7	6	5	4	3	2	1	0
ESDONE[15:8]
R

ESDONE[7:0]
R

Table 7-81 ESDONE Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	ESDONE[15:0]	R	NA	ESDONE[n] returns a 1 to indicate that the eye-scan procedure is completed on physical lane n. You must make sure that ESDONE[n] returns 1 before reading ESVO_S[n] or ECOUNT[n].

7.5.3.48 ESVO_S[15:0] Register (Offset = 0200h) [reset = NA, read-only]

ESVO_S[15:0] is shown in Figure 7-109 and described in Table 7-82.

Return to the Register Summary Table.

Eye-Scan Voltage Offset for SerDes lane n, n = 0 - 15. ESVO_S[0] is at the lowest address.

Note: Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-109 ESVO_S[15:0] Register

7	6	5	4	3	2	1	0
RESERVED		ESVO_S[n]
R		R

Table 7-82 ESVO_S[15:0] Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	NA
5-0	ESVO_S[n]	R	NA	Returns the voltage offset result from the eye-scan on physical lane n. Applies to eye-scan modes that compute the voltage offset automatically. Only valid when ESDONE[n] returns 1.

7.5.3.49 ESCOUNT[15:0] Register (Offset = 0210h) [reset = NA, read-only]

ESCOUNT[15:0] is shown in Figure 7-110 and described in Table 7-83.

Return to the Register Summary Table.

Eye-Scan Voltage Offset for SerDes lane n, n = 0 - 15. ESCOUNT[0] is at the lowest address.

Note: Only lanes 6 and 14 are connected on DDS devices. All other lanes are disconnected.

Figure 7-110 ESCOUNT[15:0] Register

7	6	5	4	3	2	1	0
ESCOUNT[15:8][n]
R

ESCOUNT[7:0][n]
R

Table 7-83 ESCOUNT[15:0] Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	ESCOUNT[n]	R	NA	Returns the mismatch count for physical lane n (applies to eye-scan modes that count mismatches). Only valid when ESDONE[n] returns 1.

7.5.3.50 LOS_TH Register (Offset = 0234h) [reset = 08h]

LOS_TH is shown in Figure 7-111 and described in Table 7-84.

Return to the Register Summary Table.

SerDes Loss-of-signal Theshold

Figure 7-111 LOS_TH Register

7	6	5	4	3	2	1	0
RESERVED				LOS_TH
R/W-0h				R/W-0h

Table 7-84 LOS_TH Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R/W

3-0

LOS_TH

R/W

Specifies the threshold for the loss-of-signal detector. Applies when LOS_EN=1. Affects all lanes.

LOS_TH : Approximate Threshold (mV)

0, 1 : RESERVED

2 - 15 : 15*(LOS_TH)

7.5.3.51 EQCNTSZ Register (Offset = 0235h) [reset = 00h]

EQCNTSZ is shown in Figure 7-112 and described in Table 7-85.

Return to the Register Summary Table.

SerDes Equalizer Counter Size

Figure 7-112 EQCNTSZ Register

7	6	5	4	3	2	1	0

R/W-0h				R/W-0h

Table 7-85 EQCNTSZ Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R/W

3-0

EQCNTSZ

R/W

Equalizer counter size: Adjusts how many votes must be accumulated to cause the adaptive equalizer gain to change. Affects all lanes. This is for debug purposes only and the user should generally not need to change this setting.

EQCNTSZ : Equalizer Vote Counter Size (votes required to adjust gain)

0 : (default) 511

1 : RESERVED

2 : 1

3 : 3

4 : 7

5 : 15

6 : 31

7 : 63

8 : 127

9 : 255

10-15 : RESERVED

7.5.3.52 CDRLOCK Register (Offset = 0238h) [reset = 00h]

CDRLOCK is shown in Figure 7-113 and described in Table 7-86.

Return to the Register Summary Table.

SerDes CDR Lock/Freeze.

Figure 7-113 CDRLOCK Register

7	6	5	4	3	2	1	0
RESERVED							CDRLOCK
R/W-00h							R/W-0b

Table 7-86 CDRLOCK Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h
0	CDRLOCK	R/W	0b	When set, the CDR is frozen and no longer tracks. When the CDR is operating in first-order mode, set CDRLOCK to freeze the CDRPHASE value to inspect it.

7.5.3.53 CDRPHASE Register (Offset = 0239h) [reset = NA, read-only]

CDRPHASE is shown in Figure 7-114 and described in Table 7-87.

Return to the Register Summary Table.

SerDes CDR Phase Status

Figure 7-114 CDRPHASE Register

7	6	5	4	3	2	1	0
CDRPHASE
R

Table 7-87 CDRPHASE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CDRPHASE	R		Returns the current CDR phase value for the lane specified by RXDLANE. It is recommended to set CDRLOCK=1 before reading this register. The format is gray-coded. Refer to CDRPHASE Status for the coding.

7.5.3.54 PLL_STATUS Register (Offset = 0250h) [reset = NA, read only]

PLL_STATUS is shown in Figure 7-67 and described in Table 7-39.

Return to the Register Summary Table.

SerDes PLL Status

Figure 7-115 PLL_STATUS Register

7	6	5	4	3	2	1	0
PLL_LOCK_STS				PLL_LOCK_LOST
R-0h				R/W1C-0h

Table 7-88 PLL_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

PLL_LOCK_STS

This field returns the LOCK signal from all four SerDes macros (3:0). This field can be used for functional (fault) testing of the PLL lock detectors.

3-0

PLL_LOCK_LOST

R/W1C

PLL_LOCK_LOST[n] is set whenever the LOCK signal from a SerDes PLL is low.

bit 0: lanes 0 - 3

bit 1: lanes 4 - 7

bit 2: lanes 8 - 11

bit 3: lanes 12 - 15

This bit is sticky (remains set even if the PLL acquires lock). Write 1 to clear a bit. These bits are for debug purposes and allow the SPI to monitor if any SerDes PLL loses lock even briefly.

7.5.3.55 JESD_RST Register (Offset = 0253h) [reset = 0x00]

JESD_RST is shown in Figure 7-116 and described in Table 7-89.

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JESD Reset

Figure 7-116 JESD_RST Register

7	6	5	4	3	2	1
RESERVED							JESD_RST
R/W-00h							R/W-0h

Table 7-89 JESD_RST Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h	RESERVED
0	JESD_RST	R/W	0b	When set, this bit holds the digital portion of the JESD circuitry in reset but does not affect the physical lane. It may be necessary to set this bit prior to setting JESD_EN = 1 and then clear this bit at a later time to start processing the JESD data. This allows the supply to settle from the large change in power that occurs when starting the PHY and JESD clocks. This is especially important if the user plans to use the LANE_ARR values, since these values are captured only the first time the elastic buffer attempts to release.

7.5.3.56 EXTREF_EN Register (Offset = 02B0h) [reset = 00h]

EXTREF_EN is shown in Figure 7-117 and described in Table 7-90.

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Enable External Reference

Figure 7-117 EXTREF_EN Register

7	6	5	4	3	2	1	0
RESERVED							EXTREF_EN
R/W-00h							R/W-0b

Table 7-90 EXTREF_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h
0	EXTREF_EN	R/W	0b	Setting this bit enable the use of an external reference voltage on the EXTREF ball.

CUR_2X_EN Register (Offset = 02B1h) [reset = 00h]

CUR_2X_EN is shown in Figure 7-118 and described in Table 7-91.

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DAC Current Doubler Enable

Figure 7-118 CUR_2X_EN Register

7	6	5	4	3	2	1	0
RESERVED							CUR_2X_EN
R/W-00h							R/W-0b

Table 7-91 CUR_2X_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h
0	CUR_2X_EN	R/W	0b	Setting this bit doubles the DAC output current.

7.5.3.57 DAC_OFS_CHG_BLK Register (Offset = 02CFh) [reset = 00h]

DAC_OFS_CHG_BLK is shown in Figure 7-119 and described in Table 7-92.

Return to the Register Summary Table.

DAC Offset Adjustment Change Block

Figure 7-119 DAC_OFS_CHG_BLK Register

7	6	5	4	3	2	1	0
RESERVED							DAC_OFS_CHG_BLK
R/W-00h							R/W-0b

Table 7-92 DAC_OFS_CHG_BLK Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1		R/W	00h
0	DAC_OFS_CHG_BLK	R/W	0b	When set, changes to DAC_OFS[n] are not propagated to the high-speed clocks and both DACs continue to use their current value. When this is changed from 1 to 0 the new DAC_OFS[n] values will be applied to both DACs in the same clock cycle.

7.5.3.58 DP_EN Register (Offset = 02E0h) [reset = 00h]

DP_EN is shown in Figure 7-120 and described in Table 7-93.

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Datapath Enable.

Figure 7-120 DP_EN Register

7	6	5	4	3	2	1	0
RESERVED							DP_EN
R/W-00h							R/W-0b

Table 7-93 DP_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

DP_EN

R/W

Setting this bit enables datapath operation. When cleared, the datapath is held in reset. This bit should be set after the chip is configured for proper operation.

Note: This register should only be changed from 0 to 1 when FUSE_DONE=1.

7.5.3.59 DUC_L Register (Offset = 02E1h) [reset = 00h]

DUC_L is shown in Figure 7-121 and described in Table 7-94.

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DUC Interpolation Factor.

Figure 7-121 DUC_L Register

7	6	5	4	3	2	1	0
RESERVED				DUC_L
R/W-0h				R/W-0h

Table 7-94 DUC_L Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R/W

3-0

DUC_L

R/W

DUC Interpolation Factor

0: 1x

1: 2x

2: 3x

3: 4x

4: 6x

5: 8x

6: 12x

7: 16x

8: 24x

9: 32x

10: 48x

11: 64x

12: 96x

13: 128x

14: 192x

15: 256x

Note: This register should only be changed when JESD_EN=0 and DP_EN=0.

7.5.3.60 DUC_GAIN Register (Offset = 02E2h) [reset = 00h]

DUC_GAIN is shown in Figure 7-122 and described in Table 7-95.

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Figure 7-122 DUC_GAIN Register

7	6	5	4	3	2	1	0
DUC_GAIN3		DUC_GAIN2		DUC_GAIN1		DUC_GAIN0
R/W-00b		R/W-00b		R/W-00b		R/W-00b

Table 7-95 DUC_GAIN Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	DUC_GAIN3	R/W	00b	DUC_GAINn adjusts the gain of DUCn (in the channel bonder) 0: 0dB 1: -6dB 2: -12dB 3: RESERVED Note: When the DUCs are configured for complex output (DUC_FORMAT=1), DUC2 and DUC3 cannot be used. In that case, DUC_GAIN2 and DUC_GAIN3 adjust the gain of the imaginary outputs of DUC0 and DUC1 respectively. Note: This register should only be changed when DP_EN=0.
5-4	DUC_GAIN2	R/W	00b
3-2	DUC_GAIN1	R/W	00b
1-0	DUC_GAIN0	R/W	00b

7.5.3.61 DUC_FORMAT Register (Offset = 02E3h) [reset = 00h]

DUC_FORMAT is shown in Figure 7-123 and described in Table 7-96.

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DUC Output Format

Figure 7-123 DUC_FORMAT Register

7	6	5	4	3	2	1	0
RESERVED							DUC_FORMAT
R/W-00h							R/W-0b

Table 7-96 DUC_FORMAT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

DUC_FORMAT

R/W

0: DUC outputs are real (DUC mixer converts complex to real by discarding the imaginary part). Up to 4 DUCs can be enabled.

1: DUC outputs are complex. Up to 2 DUCs can be enabled (DUC0 and DUC1).

Note: This register should only be changed when DP_EN=0.

7.5.3.62 DAC_SRC Register (Offset = 02E4h) [reset = 00h]

DAC_SRC is shown in Figure 7-124 and described in Table 7-97.

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DAC Source

Figure 7-124 DAC_SRC Register

7	6	5	4	3	2	1	0
DAC_SRC1				DAC_SRC0
R/W-0h				R/W-0h

Table 7-97 DAC_SRC Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

DAC_SRC1

R/W

When the DUCs are disabled (LT<=1), DAC_SRCn selects which input stream is sent to DACn. When the DUCs are enabled (LT>=2), DAC_SRCn controls which DUC outputs are routed (summed) to DACn (and the meaning of the bits depends on DUC_FORMAT).

Signals Routed to DACn when DAC_SRCn[m] is set:

LT=0.5 or 1 (DUCs disabled)

DAC_SRCn[0]: Input Stream 0 (I)

DAC_SRCn[1]: Input Stream 1 (Q)

DAC_SRCn[2]: n/a

DAC_SRCn[3]: n/a

LT is 2 or higher (DUCs enabled) Register Bit

DAC_SRCn[x] : DUC_FORMAT=0 (real) : DUC_FORMAT=1 (complex)

DAC_SRCn[0] : DUC0 (real) : DUC0 (real)

DAC_SRCn[1] : DUC1 (real) : DUC1 (real)

DAC_SRCn[2] : DUC2 (real) : DUC0 (imag)

DAC_SRCn[3] : DUC3 (real) : DUC1 (imag)

If more than one signal is routed to the same DAC, the signals are summed together. Use DUC_GAIN to avoid saturation in this case.

While it is possible to sum a real output with an imaginary output, no practical application requires that, so it is not tested or supported. When LT=0.5 or 1, no summing is supported. Only DAC_SRCn[0] or DAC_SRCn[1] should be set

Note: This register should only be changed when DP_EN=0.

3-0

DAC_SRC0

R/W

7.5.3.63 MXMODE Register (Offset = 02E8h) [reset = 00h]

MXMODE is shown in Figure 7-125 and described in Table 7-98.

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DAC Output Mode. Note: This register should only be changed when DP_EN=0.

Figure 7-125 MXMODE Register

7	6	5	4	3	2	1	0
RESERVED	MXMODE1			RESERVED	MXMODE0
R/W-0b	R/W-000b			R/W-0b	R/W-000b

Table 7-98 MXMODE Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0b
6-4	MXMODE1	R/W	000b	Specify the DAC pulse format for DACB. 0: Normal mode (non-return-to-zero or NRZ) (sinc nulls at nFS) 1: RF Mode (return to inverse or RTI) (sinc nulls at DC and 2nFS) 2: Return-to-Zero (RTZ) (sinc nulls at 2n*FS) 3: DES2X – Samples provided by the DES interpolator (low-pass mode) 4: DES2XH – Samples provided by the DES interpolator (high-pass mode) 6: Disabled – DACA is disabled 7: RESERVED
3	RESERVED	R/W	0b
2-0	MXMODE0	R/W	0b	Specify the DAC pulse format for DACA. 0: Normal mode (non-return-to-zero or NRZ) (sinc nulls at nFS) 1: RF Mode (return to inverse or RTI) (sinc nulls at DC and 2nFS) 2: Return-to-Zero (RTZ) (sinc nulls at 2n*FS) 3: DES2X – Samples provided by the DES interpolator (low-pass mode) 4: DES2XH – Samples provided by the DES interpolator (high-pass mode) 6: Disabled – DACA is disabled 7: RESERVED

7.5.3.64 TRUNC_HLSB Register (Offset = 02EAh) [reset = 00h]

TRUNC_HLSB is shown in Figure 7-126 and described in Table 7-99.

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Truncation Half LSB Offset

Figure 7-126 TRUNC_HLSB Register

7	6	5	4	3	2	1	0
RESERVED							TRUNC_HLSB
R/W-00h							R/W-0b

Table 7-99 TRUNC_HLSB Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

R/W

TRUNC_HLSB

R/W

adds ½ LSB offset for < 16-bit resolution modes or devices. For a mode or device with < 16-bit output resolution, setting this bit adds a 1/2 LSB offset to reduce the average offset introduced by truncation.

Note: This register should only be changed when DP_EN=0

7.5.3.65 TX_EN_SEL Register (Offset = 02F8h) [reset = 03h]

TX_EN_SEL is shown in Figure 7-127 and described in Table 7-100.

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Transmitter Enable Control Selection.

Figure 7-127 TX_EN_SEL Register

7	6	5	4	3	2	1	0
RESERVED				QUIET_TX_DISABLE	FAST_TX_EN	USE_TX_EN1	USE_TX_EN0
R/W-0h				R/W-0b	R/W-0b	R/W-1b	R/W-1b

Table 7-100 TX_EN_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0h
3	QUIET_TX_DISABLE	R/W	0b	0: Transmission is disabled after DEM and dither by sending a static aging safe code. For some configurations and frequencies, the outputs will have higher noise than a static mid-scale code would normally have. However, this mode has the lowest latency from transmit enable to DAC output. 1: When transmission is disabled, the input to DEM and dither is muted to minimize the output noise. This increases the latency from transmit enable to DAC output by 56 DAC clocks Note: This bit may only be set when FAST_TX_EN=1.
2	FAST_TX_EN	R/W	0b	0: When the transmit enables are both low, JESD and datapath clocks are shutdown to save power. When transmission is re-enabled the outputs remain muted until valid data is available at the output. 1: No power saving is performed and transmit enables can be used independently. Latency from transmit enable to DAC outputs is reduced in this mode.
1	USE_TX_EN1	R/W	1b	0: DACB is controlled by the TXEN1 ball. In this mode, TX_EN1 register is ignored. 1: DACB is controlled by the TX_EN1 register. In this mode the TXEN1 ball input does not affect the transmit enable for DACB. *Note: USE_TX_EN1 and USE_TX_EN0 should be programmed to the same value (individual channel control is not supported).*
0	USE_TX_EN0	R/W	1b	0: DACA is controlled by the TXEN0 ball. In this mode, TX_EN0 register is ignored. 1: DACA is controlled by the TX_EN0 register. In this mode the TXEN0 ball input does not affect the transmit enable for DACA. *Note: USE_TX_EN1 and USE_TX_EN0 should be programmed to the same value (individual channel control is not supported).*

7.5.3.66 TX_EN Register (Offset = 02F9h) [reset = 03h]

TX_EN is shown in Figure 7-128 and described in Table 7-101.

Return to the Register Summary Table.

Transmitter Enable Control

Figure 7-128 TX_EN Register

7	6	5	4	3	2	1	0
						TX_EN1	TX_EN0
R/W-00h						R/W-1b	R/W-1b

Table 7-101 TX_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R/W	00h
1	TX_EN1	R/W	1b	When USE_TX_EN1 = 1, this bit controls the transmit enable for DACB. *Note: TX_EN1 and TX_EN0 should be programmed to the same value (individual channel control is not supported).*
0	TX_EN0	R/W	1b	When USE_TX_EN0 = 1, this bit controls the transmit enable for DACA *Note: TX_EN1 and TX_EN0 should be programmed to the same value (individual channel control is not supported).*

7.5.3.67 NCO_CTRL Register (Offset = 0300h) [reset = 00h]

NCO_CTRL is shown in Figure 7-129 and described in Table 7-102.

Return to the Register Summary Table. Note: This register should only be changed when DP_EN=0.

NCO Enable

Figure 7-129 NCO_CTRL Register

7	6	5	4	3	2	1	0
FR_EN	RESERVED				NCO_SC	DDS_EN	NCO_EN
R/W-0b	R/W-0h				R/W-0b	R/W-0b	R/W-0b

Table 7-102 NCO_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	FR_EN	R/W	0b	When set, the Fast Reconfiguration (FR) interface is enabled and NCO frequency, phase, dither, and accumulator reset is controlled by the FR registers rather than the SPI registers.
6-3	RESERVED	R/W	0h
2	NCO_SC	R/W	0b	Self-Coherent NCO Mode: When this bit is set, all NCOs use the reference counter from the NCO in DDS/DUC channel 0. This is typically used along with the NCO_SS register. This only impacts phase-coherent mode (NCO_CONT=0).
1	DDS_EN	R/W	0b	When set, all DUCs are configured for DDS operation once DP_EN is set. See DDS Operation in Section 7.4.1 for details.
0	NCO_EN	R/W	0b	When set, DUC samples are mixed with the NCO.

7.5.3.68 NCO_CONT Register (Offset = 0301h) [reset = 00h]

NCO_CONT is shown in Figure 7-130 and described in Table 7-103.

Return to the Register Summary Table.

NCO Phase Continuous Mode

Figure 7-130 NCO_CONT Register

7	6	5	4	3	2	1	0
RESERVED				NCO_CONT
R/W-0h				R/W-0h

Table 7-103 NCO_CONT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R/W

3-0

NCO_CONT

R/W

For each bit NCO_CONT[n], if set, NCOn operates in phase-continuous mode. This means that frequency changes occur without seeding the phase accumulator. If the bit is clear, NCOn operates in phase-coherent mode. During frequency changes, the phase accumulator is seeded from a main counter. This means that if changing from frequency A to B and then back to A, the phase returns to what it would have been if the change never occurred.

Note: This register should only be changed when DP_EN=0.

7.5.3.69 NCO_SYNC Register (Offset = 0302h) [reset = 00h]

NCO_SYNC is shown in Figure 7-131 and described in Table 7-104.

Return to the Register Summary Table.

NCO Synchronization Configuration

Figure 7-131 NCO_SYNC Register

7	6	5	4	3	2	1	0
RESERVED						NCO_SYNC_SRC
R/W-00h						R/W-00b

Table 7-104 NCO_SYNC Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

RESERVED

R/W

00h

1-0

NCO_SYNC_SRC

R/W

00b

If FR_EN=0:

This register determines how NCO synchronization events will be triggered. This includes both accumulator resets specified by NCO_AR and the application of changes to NCO_DITH_EN, FREQ, and PHASE.

0: Setting SPI_SYNC will immediately perform specified events. (All will occur in the same clock cycle.)

1: Setting SPI_SYNC will cause the specified events to occur on the next SYSREF rising edge.

2: While SPI_SYNC is high, the specified events will occur on every SYSREF rising edge.

3: While SPI_SYNC is high, the LSb of the “I” input to DUC0 will cause the specified events. To trigger the event, the LSb must be low for 4 or more consecutive samples and then high for 4 consecutive samples. The sync will occur coincident with the 4th high sample arriving at the DUC0 input.

If FR_EN=1:

This register determines how NCO synchronization events will be triggered. This includes both accumulator resets specified by FR_NCO_AR and the application of changes to FR_NCO_DITH_EN, FR_FREQL, FR_FREQS, and FR_PHASE.

0: If FRS is set, the specified events is performed at the rising edge of FRCS. (All will occur in the same clock cycle.)

1: Reserved

2: RESERVED

3: If FRS is set, the LSb of the “I” input to DUC0 will cause the specified events following the rising edge of FRCS. To trigger the event, the LSb must be low for 4 or more consecutive samples and then high for 4 consecutive samples. The sync will occur coincident with the 4th high sample arriving at the DUC0 input. While waiting for the LSb trigger, zero will be used for the LSb data. The LSb will immediately return to being used as data after the 4th consecutive high sample.

Note: This register should only be changed when SPI_SYNC=0 and the FR interface is idle (FRCS=1).

7.5.3.70 NCO_AR Register (Offset = 0303h) [reset = 0Fh]

NCO_AR is shown in Figure 7-132 and described in Table 7-105.

Return to the Register Summary Table.

NCO Accumulator Reset

Figure 7-132 NCO_AR Register

7	6	5	4	3	2	1	0
RESERVED				NCO_AR
R/W-0h				R/W-0h

Table 7-105 NCO_AR Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

R/W

3-0

NCO_AR

R/W

For each bit NCO_AR[n], if set, the accumulator for NCOn will be reset on every sync event specified by NCO_SYNC_SRC.

Note: This register has no effect when FR_EN=1.

7.5.3.71 SPI_SYNC Register (Offset = 0304h) [reset = 00h]

SPI_SYNC is shown in Figure 7-133 and described in Table 7-106.

Return to the Register Summary Table.

SPI Sync Bit

Figure 7-133 SPI_SYNC Register

7	6	5	4	3	2	1	0
RESERVED							SPI_SYNC
R/W-00h							R/W-0b

Table 7-106 SPI_SYNC Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

SPI_SYNC

R/W

Writing ‘1’ to this register when it is ‘0’ will trigger synchronization events that are bound to this register (see NCO_SYNC_SRC). This register will return the last value written.

Note: Whether this register is edge or level sensitive depends on the setting for NCO_SYNC_SRC.

Note: This register has no effect when FR_EN=1.

NCO_SS Register (Offset = 0305h) [reset = 00h]

NCO_SS is shown in Figure 7-134 and described in Table 7-107.

Return to the Register Summary Table.

NCO_SS Bit

Figure 7-134 NCO_SS Register

7	6	5	4	3	2	1	0
RESERVED							NCO_SS
R/W-00h							R/W-0b

Table 7-107 NCO_SS Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

NCO_SS

R/W

When this bit is set, all NCOs will continuously self-synchronize every 256 DAC clock cycles.

NCO_SS can be changed while the NCOs are operating (DP_EN=1). To write a new FREQ, AMP, or PHASE value, clear NCO_SS first, and then set it again after the new values are written. All values go into effect simultaneously on all NCOs.

The user should make sure that NCO_AR=0 whenever NCO_SS=1 (otherwise the NCO accumulators and/or reference counters keep getting reset).

If the user also sets NCO_SC=1 and NCO_CONT=0, then all four NCOs maintain coherency with each other under radiation, but there may be no coherence with an external component. Each NCO accumulator is continuously seeded from the reference counter in DUC/DDS channel 0. This feature can be used to generate coherent harmonic tones to cancel out harmonic distortion in the DAC.

AMP[3:0] Register (Offset = 0318h) [reset = 0000h]

AMP[3:0] is described in Table 7-108. AMP[0] starts at address 0x0318, AMP[1] at address 0x031A, AMP[2] at address 0x031C and AMP[3] at address 0x031E.

Return to the Register Summary Table.

Table 7-108 AMP[3:0] Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

AMP[3:0]

R/W

0000h

Specifies the DDS amplitude for DDS channel n. 16-bit signed value. This register only applies to DDS Operation.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)FREQ[0] Register (Offset = 0320h) [reset = 0000000000000000h]

FREQ[0] is described in Table 7-109.

Return to the Register Summary Table.

FREQ for NCO0 Accumulator.

Table 7-109 FREQ[0] Register Field Descriptions

Bit

Field

Type

Reset

Description

63-0

FREQ[0]

R/W

0000

0000h

The NCO frequency (F_NCO) is:

F_NCO = FREQ[0] * 2^-64 * F_CLK

where F_CLK is the sample frequency of the DAC. FREQ[0] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:

FREQ[0] = 2⁶⁴ * F_NCO /F_CLK

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.73 FREQ[1] Register (Offset = 0328h) [reset = 0000000000000000h]

FREQ[1] is described in Table 7-110.

Return to the Register Summary Table.

FREQ for NCO1 Accumulator.

Table 7-110 FREQ[1] Register Field Descriptions

Bit

Field

Type

Reset

Description

63-0

FREQ[1]

R/W

0000

0000h

The NCO frequency (F_NCO) is:

F_NCO = FREQ[1] * 2^-64 * F_CLK

where F_CLK is the sample frequency of the DAC. FREQ[1] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:

FREQ[1] = 2⁶⁴ * F_NCO /F_CLK

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.74 FREQ[2] Register (Offset = 0330h) [reset = 0000000000000000h]

FREQ[2] is described in Table 7-111.

Return to the Register Summary Table.

FREQ for NCO2 Accumulator.

Table 7-111 FREQ[2] Register Field Descriptions

Bit

Field

Type

Reset

Description

63-0

FREQ[2]

R/W

0000

0000h

The NCO frequency (F_NCO) is:

F_NCO = FREQ[2] * 2^-64 * F_CLK

where F_CLK is the sample frequency of the DAC. FREQ[2] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:

FREQ[2] = 2⁶⁴ * F_NCO /F_CLK

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.75 FREQ[3] Register (Offset = 0338h) [reset = 0000000000000000h]

FREQ[3] is described in Table 7-112.

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FREQ for NCO3 Accumulator.

Table 7-112 FREQ[3] Register Field Descriptions

Bit

Field

Type

Reset

Description

63-0

FREQ[3]

R/W

0000

0000h

The NCO frequency (F_NCO) is:

F_NCO = FREQ[3] * 2^-64 * F_CLK

where F_CLK is the sample frequency of the DAC. FREQ[3] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:

FREQ[3] = 2⁶⁴ * F_NCO /F_CLK

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.76 PHASE0 Register (Offset = 0340h) [reset = 0000h]

PHASE0 is described in Table 7-113.

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Phase for NCO0 Accumulator.

Table 7-113 PHASE0 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PHASE0

R/W

Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE0* 2^-16 * 2π. This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.77 PHASE1 Register (Offset = 0342h) [reset = 0000h]

PHASE1 is described in Table 7-114.

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Phase for NCO1 Accumulator.

Table 7-114 PHASE1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PHASE1

R/W

Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE1 * 2^-16 * 2π. This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.78 PHASE2 Register (Offset = 0344h) [reset = 0000h]

PHASE2 is described in Table 7-115.

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Phase for NCO2 Accumulator.

Table 7-115 PHASE2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PHASE2

R/W

Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE2 * 2^-16 * 2π. This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

7.5.3.79 PHASE3 Register (Offset = 0346h) [reset = 0000h]

PHASE3 is described in Table 7-116.

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Phase for NCO3 Accumulator.

Table 7-116 PHASE3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PHASE3

R/W

Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE3 * 2^-16 * 2π. This register can be interpreted as signed or unsigned.

Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC.

Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)

Note: This register has no effect when FR_EN=1.

AMP_R[3:0] Register (Offset = 0378h) [reset = NA]

AMPR[3:0] is described in Table 7-117. AMP_R[0] starts at addess offset 0x0378, AMP_R[1] at address offset 0x37A, AMP_R[2] at address offset 0x37C and AMP_R[3] at address offset 0x37E

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Table 7-117 AMP_R[3:0] Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	AMP_R[n]	R	NA	This provides a readback of the amplitude setting that is currently in use by the DDS channel n. Format is 16-bit signed. This register is only applicable when DDS_EN=1. When DDS_EN=0, the return value is undefined. The value is sampled as each byte is read, so it may return incoherent data if the amplitude changes during readback.

7.5.3.80 FREQ_R0 Register (Offset = 0380h) [reset = NA, read-only]

FREQ_R0 is described in Table 7-118.

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Readback for Frequency for NCO0

Table 7-118 FREQ_R0 Register Field Descriptions

Bit	Field	Type	Reset	Description
63-0	FREQ_R0	R	NA	This provides a readback of the FREQ setting that is currently in used by the system for NCO0. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.81 FREQ_R1 Register (Offset = 0388h) [reset = NA, read-only]

FREQ_R1 is described in Table 7-119.

Return to the Register Summary Table.

Readback for Frequency for NCO1

Table 7-119 FREQ_R1 Register Field Descriptions

Bit	Field	Type	Reset	Description
63-0	FREQ_R1	R	NA	This provides a readback of the FREQ setting that is currently in used by the system for NCO1. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.82 FREQ_R2 Register (Offset = 0390h) [reset = NA, read-only]

FREQ_R2 is described in Table 7-120.

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Readback for Frequency for NCO2

Table 7-120 FREQ_R2 Register Field Descriptions

Bit	Field	Type	Reset	Description
63-0	FREQ_R2	R	NA	This provides a readback of the FREQ setting that is currently in used by the system for NCO2. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.83 FREQ_R3 Register (Offset = 0398h) [reset = NA, read-only]

FREQ_R3 is described in Table 7-121.

Return to the Register Summary Table.

Readback for Frequency for NCO3

Table 7-121 FREQ_R3 Register Field Descriptions

Bit	Field	Type	Reset	Description
63-0	FREQ_R3	R	NA	This provides a readback of the FREQ setting that is currently in used by the system for NCO3. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.84 PHASE_R0 Register (Offset = 03A0h) [reset = NA, read-only]

PHASE_R0 is described in Table 7-122.

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Readback for Phase Word for NCO0

Table 7-122 PHASE_R0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PHASE_R0	R/W	0h	This provides a readback of the PHASE setting that is currently in used by the system for NCO0. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.85 PHASE_R1 Register (Offset = 03A2h) [reset = NA, read-only]

PHASE_R1 is described in Table 7-123.

Return to the Register Summary Table.

Readback for Phase Word for NCO1

Table 7-123 PHASE_R1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PHASE_R1	R/W	NA	This provides a readback of the PHASE setting that is currently in used by the system for NCO1. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.86 PHASE_R2 Register (Offset = 03A4h) [reset = NA, read-only]

PHASE_R2 is described in Table 7-124.

Return to the Register Summary Table.

Readback for Phase Word for NCO2

Table 7-124 PHASE_R2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PHASE_R2	R/W	NA	This provides a readback of the PHASE setting that is currently in used by the system for NCO2. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.87 PHASE_R3 Register (Offset = 03A6h) [reset = NA, read-only]

PHASE_R3 is described in Table 7-125.

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Readback for Phase Word for NCO3

Table 7-125 PHASE_R3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PHASE_R3	R/W	NA	This provides a readback of the PHASE setting that is currently in used by the system for NCO3. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

7.5.3.88 FR_FRS_R Register (Offset = 03E0h) [reset = NA, read-only]

FR_FRS_R is shown in Figure 7-135 and described in Table 7-126.

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Readback for FR Syncrhonization

Figure 7-135 FR_FRS_R Register

7	6	5	4	3	2	1	0
FR_FRS_R	RESERVED
R	R

Table 7-126 FR_FRS_R Register Field Descriptions

Bit

Field

Type

Reset

Description

FR_FRS_R

This provides readback for the value of FRS in the last transaction.

Note: This value is not synchronized and should only be read while the FR interface is static.

6-0

RESERVED

7.5.3.89 FR_NCO_AR_R Register (Offset = 03E1h) [reset = NA, read-only]

FR_NCO_AR_R is shown in Figure 7-136 and described in Table 7-127.

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Readback for FR NCO Accumulator Reset

Figure 7-136 FR_NCO_AR_R Register

7	6	5	4	3	2	1	0
RESERVED				FR_NCO_AR_R
R				R

Table 7-127 FR_NCO_AR_R Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

3-0

FR_NCO_AR_R

This provides readback for the last value that was written to FR_NCO_AR.

Note: This value is not synchronized and should only be read while the FR interface is static.

7.5.3.90 TS_TEMP Register (Offset = 0400h) [reset = NA, read-only]

TS_TEMP is shown in Figure 7-137 and described in Table 7-128.

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Temperature Reading in Celsius

Figure 7-137 TS_TEMP Register

7	6	5	4	3	2	1	0
TS_TEMP
R

Table 7-128 TS_TEMP Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

TS_TEMP

Returns the temperature sensor reading. This returns an unsigned value from 0 to 255. Subtract 80 from this value to get degrees Celsius. For example, a value of 110 indicates 30C.

See Temperature Sensor.

Note: Reads of this register require slower SPI timing. See Switching Characteristics.

Note: This register will not return valid data unless TS_SLEEP=0.

7.5.3.91 TS_SLEEP Register (Offset = 0401h) [reset = 00h]

TS_SLEEP is shown in Figure 7-138 and described in Table 7-129.

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Temperature Sensor Sleep

Figure 7-138 TS_SLEEP Register

7	6	5	4	3	2	1	0
RESERVED							TS_SLEEP
R/W-00h							R/W-0b

Table 7-129 TS_SLEEP Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	00h
0	TS_SLEEP	R/W	0b	If temperature conversions are not needed, set this bit to sleep the temperature sensor.

7.5.3.92 SYNC_STATUS Register (Offset = 0410h) [reset = NA]

SYNC_STATUS is shown in Figure 7-139 and described in Table 7-130.

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Synchronization Status

Figure 7-139 SYNC_STATUS Register

7	6	5	4	3	2	1	0
RESERVED				CLK_REALIGNED	CLK_ALIGNED	NCO_SYNC_DET	SYSREF_DET
R				R/W1C	R	R/W1C	R/W1C

Table 7-130 SYNC_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	NA
3	CLK_REALIGNED	R/W1C	NA	This bit is set any time the clock dividers associated with SYSREF (excluding LMFC/LEMC) are realigned to SYSREF. This bit is useful to confirm the internally sampled SYSREF signal has a correct and stable period in DDS mode (or for debug purposes in JESD204C mode). Write a 1 to clear this bit.
2	CLK_ALIGNED	R	NA	When set, indicates that the last SYSREF pulse was consistent with the SYSREF-associated clock dividers (except for the LMFC/LEMC). Since the LMFC/LEMC does not affect this bit, it is appropriate to use in DDS mode, but can also be used when the JESD204C interface is enabled. This bit is read-only (cannot be cleared via SPI).
1	NCO_SYNC_DET	R/W1C	NA	This bit is set any time one or more NCOs receives a sync event. Write a 1 to clear this bit.
0	SYSREF_DET	R/W1C	NA	This bit is set when a SYSREF is detected. Write a 1 to clear the bit and allow it to be re-detected.

7.5.3.93 SYS_ALM Register (Offset = 0430h) [reset = NA, read/write 1 to clear]

SYS_ALM is shown in Figure 7-140 and described in Table 7-131.

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System Alarm Status

Figure 7-140 SYS_ALM Register

7	6	5	4	3	2	1	0
JESD_LINK_DOWN_ALM	JTIMER_EXPIRED_ALM	JESD_CRC_ALM	RESERVED			SYSRST_ALM	SYSREF_ALM
R/W1C	R/W1C	R/W1C	R			R/W1C	R/W1C

Table 7-131 SYS_ALM Register Field Descriptions

Bit	Field	Type	Description
7	JESD_LINK_DOWN_ALM	R/W1C	This bit is set any time LINK_UP transitions from 1 to 0 while JESD_EN=1. Write 1 to clear the alarm.
6	JTIMER_EXPIRED_ALM	R/W1C	This bit is set if the JESD link has been down (LINK_UP=0 while JESD_EN=1) longer than allowed by JTIMER. Write 1 to clear the alarm.
5	JESD_CRC_ALM	R/W1C	This bit is set any time CRC_FAULT is detected on an enabled lane. Applies only to 64b/66b modes. Write 1 to clear the alarm.
4-2	RESERVED	R
1	SYSRST_ALM	R/W1C	This bit is set any time the chip is reset due to the RESET ball, power on reset, or SOFT_RESET. Write 1 to clear the alarm.
0	SYSREF_ALM	R/W1C	This bit is set any time a SYSREF edge is detected at an incorrect alignment by either the clock dividers or by the JESD Subsystem (when JESD_EN=1). Write 1 to clear the alarm.

7.5.3.94 ALM_MASK Register (Offset = 0431h) [reset = 00h]

ALM_MASK is shown in Figure 7-141 and described in Table 7-132.

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Alarm Mask

Figure 7-141 ALM_MASK Register

7	6	5	4	3	2	1	0
JESD_LINK_DOWN_MASK	JTIMER_EXPIRED_MASK	JESD_CRC_MASK	RESERVED				SYSREF_ALM_MASK
R/W-0b	R/W-0b	R/W-0b	R/W-0h				R/W-0b

Table 7-132 ALM_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
7	JESD_LINK_DOWN_MASK	R/W	0h	When set, alarms from the JESD_LINK_DOWN_ALM register are masked and will not impact the alarm output.
6	JTIMER_EXPIRED_MASK	R/W	0b	When set, alarms from the JTIMER_EXPIRED_ALM register are masked and will not impact the alarm output.
5	JESD_CRC_MASK	R/W	0b	When set, alarms from the JESD_CRC_ALM register are masked and will not impact the alarm output.
4-1	RESERVED	R/W	0h
0	SYSREF_ALM_MASK	R/W	0b	When set, alarms from the SYSREF_ALM register are masked and will not impact the alarm output.

7.5.3.95 MUTE_MASK Register (Offset = 0432h) [reset = 21h]

MUTE_MASK is shown in Figure 7-142 and described in Table 7-133.

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DAC Mute Mask

Figure 7-142 MUTE_MASK Register

7	6	5	4	3	2	1	0
RESERVED		JESD_CRC_MUTE_MASK	RESERVED				SYSREF_MUTE_MASK
R/W-00b		R/W-1b	R/W-0h				R/W-1b

Table 7-133 MUTE_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00b
5	JESD_CRC_MUTE_MASK	R/W	1b	JESD CRC alarms will mute the DACs according to JESD_CRC_REC unless this bit is set.
4-1	RESERVED	R/W	0h
0	SYSREF_MUTE_MASK	R/W	1b	Alarms from the SYSREF_ALM register will mute the DACs unless this bit is set.

7.5.3.96 MUTE_REC Register (Offset = 0433h) [reset = A0h]

MUTE_REC is shown in Figure 7-143 and described in Table 7-134.

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DAC Mute Recovery

Figure 7-143 MUTE_REC Register

7	6	5	4	3	2	1	0
JESD_LINK_DOWN_REC	RESERVED	JESD_CRC_REC	RESERVED
R/W-1b	R/W-0b	R/W-1b	R/W-00h

Table 7-134 MUTE_REC Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	JESD_LINK_DOWN_REC	R/W	1b	0: DAC will remain muted until the JESD_LINK_DOWN_ALM = 0. 1: DAC will unmute automatically when the JESD link recovers.
6	RESERVED	R/W	0b
5	JESD_CRC_MUTE_MASK	R/W	1b	This bit is only used if JESD_CRC_MUTE_MASK = 0. 0: DAC will remain muted until the JESD_CRC_ALM=0 1: DAC will unmute automatically when CRC_FAULT=0.
4-0	RESERVED	R/W	0h

7.5.3.97 FUSE_STATUS Register (Offset = 0600h) [reset = NA]

FUSE_STATUS is shown in Figure 7-142 and described in Table 7-133.

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Fuse Status

Figure 7-144 FUSE_STATUS Register

7	6	5	4	3	2	1	0
RESERVED							FUSE_DONE
R-NA							R-NA

Table 7-135 FUSE_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	NA
0	FUSE_DONE	R	NA	Returns ‘1’ when the fuse controller is idle, meaning the controller has completed the fuse auto-load sequence. The sequence takes less than 523,000 CLK cycles to complete, or FUSE_DONE can be polled until it is '1'. When FUSE_DONE is ‘0’ the user should not read or write any fuse-backed registers.

7.5.3.98 FINE_CUR_A Register (Offset = 0723h) [reset = varies]

FINE_CUR_A is shown in Figure 7-145 and described in Table 7-136.

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Fine Bias Current Control for DACA

Figure 7-145 FINE_CUR_A Register

7	6	5	4	3	2	1	0
RESERVED		FINE_CUR_A
R-00b		R/W-varies

Table 7-136 FINE_CUR_A Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	00b
5-0	FINE_CUR_A	R/W	varies	Fine current control setting for DAC A. See Section 7.3.2.2. The default values varies to match output current specification.

7.5.3.99 COARSE_CUR_A Register (Offset = 0724h) [reset = 0Fh]

COARSE_CUR_A is shown in Figure 7-146 and described in Table 7-137.

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Coarse Bias Current Control for DACA

Figure 7-146 COARSE_CUR_A Register

7	6	5	4	3	2	1	0
DAC0_CBIAS_SLEEP				COARSE_CUR_A
R/W-0h				R/W-0xF

Table 7-137 COARSE_CUR_A Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DAC0_CBIAS_SLEEP	R/W	0h	DAC coarse current setting during sleep. See discussion for DC coupled outputs in Section 8.1.6
3-0	COARSE_CUR_A	R/W	0xF	Coarse current control setting for DAC A. See Section 7.3.2.2.

7.5.3.100 FINE_CUR_B Register (Offset = 0725h) [reset = varies]

FINE_CUR_B is shown in Figure 7-147 and described in Table 7-138.

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Fine Bias Current Control for DAC B

Figure 7-147 FINE_CUR_B Register

7	6	5	4	3	2	1	0
RESERVED		FINE_CUR_B
R-00b		R/W-varies

Table 7-138 FINE_CUR_B Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	00b
5-0	FINE_CUR_B	R/W	varies	Fine current control setting for DAC B. See Section 7.3.2.2. The default values varies to match output current specification.

7.5.3.101 COARSE_CUR_B Register (Offset = 0726h) [reset = 0Fh]

COARSE_CUR_B is shown in Figure 7-148 and described in Table 7-139.

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Coarse Bias Current Control for DACB

Figure 7-148 COARSE_CUR_B Register

7	6	5	4	3	2	1	0
DAC1_CBIAS_SLEEP				COARSE_CUR_B
R/W-0h				R/W-0xF

Table 7-139 COARSE_CUR_B Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DAC1_CBIAS_SLEEP	R/W	0h	DAC coarse current setting during sleep. See discussion for DC coupled outputs in Section 8.1.6
3-0	COARSE_CUR_B	R/W	0xF	Coarse current control setting for DAC B. See Section 7.3.2.2.

7.5.3.102 DEM_ADJ Register (Offset = 0727h) [reset = 11h]

DEM_ADJ is shown in Figure 7-148 and described in Table 7-139.

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DEM Adjust

Table 7-140 Single Edge DEM Adjust

7	6	5	4	3	2	1	0
DEM_ADJ1				DEM_ADJ0
R/W-0x1				R/W-0x1

Table 7-141 DEM_ADJ Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	DEM_ADJ1	R/W	0x1	Adjust DEM behavior for single-edge data-independent DEM for DAC1. This register has no effect unless DAC1 is configured for single-edge data-independent DEM. Only 0 to 3 are valid settings, 4 through 15 are reserved.
3-0	DEM_ADJ0	R/W	0x1	Adjust DEM behavior for single-edge data-independent DEM for DAC0. This register has no effect unless DAC0 is configured for single-edge data-independent DEM. Only 0 to 3 are valid settings, 4 through 15 are reserved.

7.5.3.103 DEM_DITH Register (Offset = 0729h) [reset = 00h]

DEM_DITH is shown in Figure 7-149 and described in Table 7-142.

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DAC DEM and Dither Control

Figure 7-149 DEM_DITH Register

7	6	5	4	3	2	1	0
DEM_DACB		DEM_DACA		DITHER_DACB		DITHER_DACA
R/W-00b		R/W-00b		R/W-00b		R/W-00b

Table 7-142 DEM_DITH Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	DEM_DACB	R/W	00b	0 : Enable single-edge, data-independent DEM for DACB 1 : Enable dual-edge, data-independent DEM for DACB 2 : Enable data-dependent DEM for DACB 3 : DEM disabled for DACB
5-4	DEM_DACA	R/W	00b	0 : Enable single-edge, data-independent DEM for DACA 1 : Enable dual-edge, data-independent DEM for DACA 2 : Enable data-dependent DEM for DACA 3 : DEM disabled for DACA
3-2	DITHER_DACB	R/W	00b	0 : Enable single-edge dithering for DACB 1 : Enable dual-edge dithering for DACB 2 : RESERVED 3 : Dithering disabled for DACB
1-0	DITHER_DACA	R/W	00b	0 : Enable single-edge dithering for DACA 1 : Enable dual-edge dithering for DACA 2 : RESERVED 3 : Dithering disabled for DACA

7.5.3.104 DAC_OFS[0:1] Register (Offset = 072Ah) [reset = 00h]

DAC_OFS[0:1] is described in Table 7-143.

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DAC Offset Control. DAC_OFS[0] is at the lowest address.

Table 7-143 DAC_OFS[0:1] Register Field Descriptions

Bit

Field

Type

Reset

Description

15-13

Reserved

R/W

000b

12-0

DAC_OFS[n]

R/W

00b

Offset adjustment for DACn (n = 0 or 1). The value in this register is added to the DACn output. This is a 2’s complement, 13-bit signed value. The LSB weight is one DAC LSB.

The value programmed into this register passes through a saturation function to limit the adjustment to what is possible. If dithering is enabled on DACn (see DEM_DITH), DAC_OFS[n] is saturated to the range +/- 128. If dithering is disabled on DACn, the saturation range is +/-3968.

See Section 7.3.4.

Note: This value should only be changed when DP_EN=0 or DAC_OFS_CHG_BLK=1.