JAJSVE5 September   2024 DDS39RF12 , DDS39RFS12

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Single Tone Spectra
    12. 6.12 Typical Characteristics: Dual Tone Spectra
    13. 6.13 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Understanding Dual Edge Sampling Modes
      4. 8.1.4 Eye Scan Procedure
      5. 8.1.5 Pre/Post Cursor Analysis Procedure
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Detailed Clocking Subsystem Design Procedure
        1. 8.2.4.1 Example 1: SWAP-C Optimized
        2. 8.2.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO
        3. 8.2.4.3 Example 3: Discrete Analog PLL for Best DAC Performance
        4. 8.2.4.4 10GHz Clock Generation
      5. 8.2.5 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 商標
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 FCBGA Package, 256-Ball Flip Chip BGA with 1mm pitch ( Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
DAC Outputs
DACOUTA- A13 O DAC channel A analog output negative terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance.
DACOUTA+ A12 O DAC channel A analog output positive terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance.
DACOUTB- T13 O DAC channel B analog output negative terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance. Not available in single channel devices.
DACOUTB+ T12 O DAC channel B analog output positive terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance. Not available in single channel devices.
Differential Clock and SYSREF Inputs
CLK- E16 I Device clock input negative terminal. There is an internal 100Ω differential termination between CLK+ and CLK–. This input is self-biased and should be AC coupled to the clock source.
CLK+ D16 I Device clock input positive terminal. There is an internal 100Ω differential termination between CLK+ and CLK–. This input is self-biased and should be AC coupled to the clock source.
SYSREF- N16 I Differential JESD204C SYSREF input negative terminal. There is an internal 100Ω differential termination between SYSREF+ and SYSREF–.
SYSREF+ M16 I Differential JESD204C SYSREF input negative terminal. There is an internal 100Ω differential termination between SYSREF+ and SYSREF–.
SerDes Interface
6SRX- G1 I Serdes Lane 6 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 6SRX+.
6SRX+ F1 I Serdes Lane 6 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 6SRX-.
14SRX- L1 I Serdes Lane 14 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 14SRX+.
14SRX+ K1 I Serdes Lane 14 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 14SRX-.
GPIO Functions
ALARM H4 O ALARM pin is asserted when an internal unmasked alarm is detected. Alarm mask is set by ALM_MASK register.
FRCLK F4 I Fast reconfiguration interface clock.
FRCS G4 I Fast reconfiguration interface chip select. Internal pullup.
FRDI0 E4 I Fast reconfiguration interface data bit 0.
FRDI1 E5 I Fast reconfiguration interface data bit 1.
FRDI2 F5 I Fast reconfiguration interface data bit 2.
FRDI3 G5 I Fast reconfiguration interface data bit 3.
RESET D6 I Device reset input, active low. Must be toggled after power up. Internal pullup.
SCANEN E6 I TI use only, can be left unconnected. Internal pulldown.
SCLK E8 I Serial programming interface (SPI) clock input.
SCS E7 I Serial programming interface (SPI) device select input, active low. Internal pullup.
SDI D8 I Serial programming interface (SPI) data input.
SDO D7 O Serial programming interface (SPI) data output. High impedance when not reading out SPI data.
SYNC J4 O JESD204C SYNC output, active low.
TXEN0 D5 I Transmit enable for channel A active high input. This pin must be enabled using register USE_TX_EN0. The DAC output is forced to midcode (0x0000 in 2's complement) when transmission is disabled. Internal pullup.
TXEN1 D4 I Transmit enable for channel B active high input. This pin must be enabled using register USE_TX_EN1. The DAC output is forced to midcode (0x0000 in 2's complement) when transmission is disabled. Internal pullup.
Analog functions
ATEST N6 O Analog test pin for TI use. Should be left disconnected.
EXTREF J15 I/O Reference voltage output or input, determined by the EXTREF_EN register field. If the internal reference is used, the ball should be tied through 0.1uF to AGND.
RBIAS- H16 O Full-scale output current bias is set by the resistor tied from this terminal to RBIAS+.
RBIAS+ J16 O Full-scale output current bias is set by the resistor tied from this terminal to RBIAS-.
RTEST M5 O TI use only. Tie to AGND.
Power Supplies
VDDA18A G14 H14 I 1.8V supply voltage for DAC channel A. Can be combined with VDDA18B, but may degrade channel-to-channel crosstalk (XTALK).
VDDA18B J14 K14 I 1.8V supply voltage for DAC channel B. Can be combined with VDDA18A, but may degrade channel-to-channel crosstalk (XTALK).
VDDCLK10 F11 H11 J11 L11 E12 M12 I 1V supply voltage for internal sampling clock distribution path. Noise or spurs on this supply may degrade phase noise performance. Recommended to separate from VDDDIG and VDDA for best performance.
VDDCLK18 H12 H13 I 1.8V supply voltage for clock (CLK+/–) input buffer. Noise or spurs on this supply may degrade phase noise performance.
VDDDIG F7 H7 J7 L7 N7 G8 K8 M8 I 1V supply voltage for digital block. Recommended to separate from VDDA and VDDCLK for best performance.
VDDEA F8 F9 I 1V supply voltage for channel A DAC encoder. Recommended to separate from VDDDIG for best performance. Can be combined with VDDEB.
VDDEB L8 L9 I 1V supply voltage for channel B DAC encoder. Recommended to separate from VDDDIG for best performance. Can be combined with VDDEA.
VDDIO D9 E9 I 1.8V supply for CMOS input and output terminals.
VDDLA F10 H10 I 1V supply for DAC analog latch for channel A. Separate from VDDLB for best channel-to-channel crosstalk (XTALK). Must be separated from VDDDIG for best performance.
VDDLB J10 L10 I 1V supply for DAC analog latch for channel B. Separate from VDDLA for best channel-to-channel crosstalk (XTALK). Must be separated from VDDDIG for best performance.
VDDR18 K4 L4 M4 N4 I 1.8V Supply voltage for SerDes receivers.
VDDSYS18 J12 J13 I 1.8V supply voltage for SYSREF (SYSREF+/–) input buffer. Can be combined with VDDCLK18 when SYSREF is disabled during normal operation. This supply should be separate from VDDCLK18 when SYSREF is run continuously during operation to avoid noise and spur coupling and reduced phase noise performance.
VDDT C3 D3 F3 G3 K3 L3 N3 P3 C4 P4 C5 H5 J5 P5 G6 K6 M6 C7 P7 C8 P8 I 1V Supply voltage for SerDes termination.
VEEAM18 C11 D11 C12 D12 C13 D13 I –1.8V supply voltage for DAC current source bias for channel A. Can be combined with VEEBM18, but may degrade channel-to-channel crosstalk (XTALK).
VEEBM18 N11 P11 N12 P12 N13 P13 I –1.8V supply voltage for DAC current source bias for channel B. Can be combined with VEEAM18, but may degrade channel-to-channel crosstalk (XTALK).
VQPS N9 P9 I TI use only. Can be tied to DGND during normal operation.
Grounds
AGND A10 B10 C10 D10 N10 P10 R10 T10 A11 B11 R11 T11 B12 R12 B13 G13 K13 R13 A14 B14 C14 D14 N14 P14 R14 T14 G15 H15 K15 G16 K16 - Analog ground.
DGND A1 B1 C1 D1 E1 H1 J1 M1 N1 P1 R1 T1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 A3 B3 E3 H3 J3 M3 R3 T3 A4 B4 R4 T4 A5 B5 K5 L5 N5 R5 T5 A6 B6 C6 F6 H6 J6 L6 P6 R6 T6 A7 B7 G7 K7 M7 R7 T7 A8 B8 H8 J8 N8 R8 T8 A9 B9 C9 G9 H9 J9 K9 M9 R9 T9 - Digital ground.
VSSCLK E10 G10 K10 M10 E11 G11 K11 M11 F12 G12 K12 L12 E13 F13 L13 M13 E14 F14 L14 M14 A15 B15 C15 D15 E15 F15 L15 M15 N15 P15 R15 T15 A16 B16 C16 F16 L16 P16 R16 T16 - Clock ground.