JAJSVE5 September 2024 DDS39RF12 , DDS39RFS12
PRODUCTION DATA
The range of values for RBD depends on the phase delta between the Rx and Tx LMFC/LEMC, as well as link latencies in the Tx, channel, and Rx. Therefore, do not provide a pre-determined RBD value that is appropriate for all systems. The LANE_ARR registers are provided to help the user measure lane arrival times and select an appropriate RBD value for the system. For deterministic latency, the RBD value can be selected during system prototyping and stored in system firmware. Calculating RBD each time the system is turned on can result in non-deterministic latency.
The arrival times are reported in units of quad-bytes and are measured with respect to a modulo-64 reference counter that increments for each quad-byte received (per lane). The reference counter is aligned (reset) by SYSREF.
Since the lane arrival times are modulo-values, it is important to use arithmetic that accounts for the modulus (the latest arriving lane might actually have a smaller LANE_ARR value than the earliest arriving lane). Figure 7-55 and Figure 7-56 depict the RBD calculation graphically to emphasize this. The lane arrival times are mapped onto a circle with a circumference of 64 quad-bytes which corresponds to the modulo-64 counter used to measure lane arrival times.
The earliest usable RBD value is equal to the latest LANE_ARR value plus 1 (modulo 64). The latest usable RBD value is equal to the earliest LANE_ARR value plus the buffer depth (modulo 64) (the buffer depth is 16 quad-octets, except when K x F = 32, then the buffer depth is reduced to 8 quad-octets). Note that the latest, usable RBD value causes the earliest arriving lane to overwrite buffer data on the same clock cycle that the data is being read out (this is acceptable and does not cause overflow).
Choosing an RBD value in the middle of the usable range maximizes the skew tolerance; however, the user can choose a value closer to the latest arriving lane if lower latency is desired.