JAJSD57F February 2006 – September 2016 DIX4192
PRODUCTION DATA.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AESOUT | 34 | O | DIT buffered AES3-encoded data |
AGND | 10 | GND | DIR comparator and PLL power-supply ground |
BCKA | 37 | I/O | Audio serial port A bit clock |
BCKB | 48 | I/O | Audio serial port B bit clock |
BGND | 44 | GND | Substrate ground, connect to AGND (pin 10) |
BLS | 35 | I/O | DIT block start clock |
CCLK/SCL | 20 | I | Serial data clock for SPI mode or I2C mode |
CDIN/A1 | 21 | I | SPI port serial data input or programmable slave address for I2C mode |
CDOUT/SDA | 22 | I/O | SPI port serial data output (tri-state output) or serial data I/O for I2C mode |
CPM | 18 | I | Control port mode, 0 = SPI mode, 1 = I2C mode |
CS/A0 | 19 | I | Chip select (active low) for SPI mode or programmable slave address for I2C mode |
DGND1 | 16 | GND | Digital core ground |
DGND2 | 30 | GND | DIR line receiver bias and DIT line driver digital ground |
DGND3 | 43 | GND | Logic I/O ground |
GPO1 | 26 | O | General-purpose output 1 |
GPO2 | 27 | O | General-purpose output 2 |
GPO3 | 28 | O | General-purpose output 3 |
GPO4 | 29 | O | General-purpose output 4 |
INT | 23 | O | Interrupt flag (open-drain, active low) |
LOCK | 11 | O | DIR PLL lock flag (active low) |
LRCKA | 38 | I/O | Audio serial Port A left/right clock |
LRCKB | 47 | I/O | Audio serial Port B left/right clock |
MCLK | 25 | I | Master clock |
NC | 14, 15, 41 | — | No internal signal connection, internally bonded to ESD pad |
RST | 24 | I | Reset (active low) |
RX1+ | 1 | I | Line receiver 1, noninverting input |
RX1– | 2 | I | Line receiver 1, inverting input |
RX2+ | 3 | I | Line receiver 2, noninverting input |
RX2– | 4 | I | Line receiver 2, inverting input |
RX3+ | 5 | I | Line receiver 3, noninverting input |
RX3– | 6 | I | Line receiver 3, inverting input |
RX4+ | 7 | I | Line receiver 4, noninverting input |
RX4– | 8 | I | Line receiver 4, inverting input |
RXCKI | 13 | I | DIR reference clock |
RXCKO | 12 | O | DIR recovered master clock (tri-state output) |
SDINA | 39 | I | Audio serial Port A data input |
SDINB | 46 | I | Audio serial Port B data input |
SDOUTA | 40 | O | Audio serial Port A data output |
SDOUTB | 45 | O | Audio serial Port B data output |
SYNC | 36 | O | DIT internal sync clock |
TX+ | 32 | O | DIT line driver noninverting output |
TX– | 31 | O | DIT line driver inverting output |
VCC | 9 | PWR | DIR comparator and PLL power supply, 3.3-V nominal |
VDD18 | 17 | PWR | Digital core supply, 1.8-V nominal |
VDD33 | 33 | PWR | DIR line receiver bias and DIT line driver supply, 3.3-V nominal |
VIO | 42 | PWR | Logic I/O supply, 1.65 V to 3.6 V |