JAJSN51 データシート

JAJSN51C november 2021 – july 2023 DLP160AP

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FQT|42
- MCLG043

サーマルパッド・メカニカル・データ

発注情報

jajsn51c_oa

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS⁽²⁾	MIN	TYP	MAX	UNIT
CURRENT
I_DD	Supply current: V_DD⁽³⁾ ⁽⁴⁾	V_DD = 1.95 V			50	mA
I_DD	Supply current: V_DD⁽³⁾ ⁽⁴⁾	V_DD = 1.8 V		38		mA
I_DDI	Supply current: V_DDI⁽³⁾ ⁽⁴⁾	V_DDI = 1.95 V			12	mA
I_DDI	Supply current: V_DDI⁽³⁾ ⁽⁴⁾	V_DDI = 1.8 V		8		mA
I_OFFSET	Supply current: V_OFFSET⁽⁵⁾ ⁽⁶⁾	V_OFFSET = 10.5 V			1	mA
I_OFFSET	Supply current: V_OFFSET⁽⁵⁾ ⁽⁶⁾	V_OFFSET = 10 V		0.9		mA
I_BIAS	Supply current: V_BIAS⁽⁵⁾ ⁽⁶⁾	V_BIAS = 18.5 V			0.2	mA
I_BIAS	Supply current: V_BIAS⁽⁵⁾ ⁽⁶⁾	V_BIAS = 18 V		0.18		mA
I_RESET	Supply current: V_RESET⁽⁶⁾	V_RESET = –14.5 V			-0.9	mA
I_RESET	Supply current: V_RESET⁽⁶⁾	V_RESET = –14 V		-0.8		mA
POWER⁽⁷⁾
P_DD	Supply power dissipation: V_DD⁽³⁾ ⁽⁴⁾	V_DD = 1.95 V			97.5	mW
P_DD	Supply power dissipation: V_DD⁽³⁾ ⁽⁴⁾	V_DD = 1.8 V		68.4		mW
P_DDI	Supply power dissipation: V_DDI⁽³⁾ ⁽⁴⁾	V_DDI = 1.95 V			23.4	mW
P_DDI	Supply power dissipation: V_DDI⁽³⁾ ⁽⁴⁾	V_DD = 1.8 V		14.4		mW
P_OFFSET	Supply power dissipation: V_OFFSET⁽⁵⁾ ⁽⁶⁾	V_OFFSET = 10.5 V			10.5	mW
P_OFFSET	Supply power dissipation: V_OFFSET⁽⁵⁾ ⁽⁶⁾	V_OFFSET = 10 V		9		mW
P_BIAS	Supply power dissipation: V_BIAS⁽⁵⁾ ⁽⁶⁾	V_BIAS = 18.5 V			3.7	mW
P_BIAS	Supply power dissipation: V_BIAS⁽⁵⁾ ⁽⁶⁾	V_BIAS = 18 V		3.2		mW
P_RESET	Supply power dissipation: V_RESET⁽⁶⁾	V_RESET = –14.5 V			13.1	mW
P_RESET	Supply power dissipation: V_RESET⁽⁶⁾	V_RESET = –14 V		11.2		mW
P_TOTAL	Supply power dissipation: Total			106	148	mW
LPSDR INPUT⁽⁸⁾
V_IH(DC)	DC input high voltage⁽⁹⁾		0.7 × V_DD		V_DD + 0.3	V
V_IL(DC)	DC input low voltage⁽⁹⁾		–0.3		0.3 × V_DD	V
V_IH(AC)	AC input high voltage⁽⁹⁾		0.8 × V_DD		V_DD + 0.3	V
V_IL(AC)	AC input low voltage⁽⁹⁾		–0.3		0.2 × V_DD	V
∆V_T	Hysteresis ( V_T+ – V_T– )	Figure 6-10	0.1 × V_DD		0.4 × V_DD	V
I_IL	Low–level input current	V_DD = 1.95 V; V_I = 0 V	–100			nA
I_IH	High–level input current	V_DD = 1.95 V; V_I = 1.95 V			100	nA
LPSDR OUTPUT⁽¹⁰⁾
V_OH	DC output high voltage	I_OH = –2 mA	0.8 × V_DD			V
V_OL	DC output low voltage	I_OL = 2 mA			0.2 × V_DD	V
CAPACITANCE
C_IN	Input capacitance LPSDR	ƒ = 1 MHz			10	pF
C_IN	Input capacitance SubLVDS	ƒ = 1 MHz			10	pF
C_OUT	Output capacitance	ƒ = 1 MHz			10	pF
C_RESET	Reset group capacitance	ƒ = 1 MHz; (640 ×360 micromirrors)	90		140	pF

(1) Device electrical characteristics are over Section 6.4 unless otherwise noted.

(2) All voltage values are with respect to the ground pins (V_SS).

(3) To prevent excess current, the supply voltage delta |V_DDI – V_DD| must be less than the specified limit.

(4) Supply power dissipation based on non–compressed commands and data.

(5) To prevent excess current, the supply voltage delta |V_BIAS – V_OFFSET| must be less than the specified limit.

(6) Supply power dissipation based on 3 global resets in 300 µs.

(7) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, V_RESET. All V_SS connections are also required.

(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) LPSDR specification is for pin LS_RDATA.