JAJSN52D October   2021  – October 2024 DLP160CP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
    8. 5.8  Switching Characteristics
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application—nHD Mode
      2. 7.2.2 Typical Application—HD Mode
      3. 7.2.3 Design Requirements
      4. 7.2.4 Detailed Design Procedure
      5. 7.2.5 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply Power-Up Procedure
    2. 8.2 Power Supply Power-Down Procedure
    3. 8.3 Power Supply Sequencing Requirements
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Device Nomenclature
      3. 10.1.3 Device Markings
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 FQT Package 35-Pin
DLP160CP
Table 4-1 Connector Pins
PIN(1)PACKAGE NET LENGTH (mm)(2)
NAMENO.TYPESIGNALDATA RATEDESCRIPTION
DATA INPUTS
D_N(0)A2ISubLVDSDoubleData, negative1.91
D_N(1)A4ISubLVDSDoubleData, negative3.6
D_N(2)D4ISubLVDSDoubleData, negative3.28
D_N(3)E2ISubLVDSDoubleData, negative1.67
D_P(0)A3ISubLVDSDoubleData, positive2.03
D_P(1)B4ISubLVDSDoubleData, positive3.7
D_P(2)E4ISubLVDSDoubleData, positive3.39
D_P(3)E3ISubLVDSDoubleData, positive1.77
DCLK_NC3ISubLVDSDoubleClock, negative2.29
DCLK_PC4ISubLVDSDoubleClock, positive2.4
CONTROL INPUTS
LS_WDATAC12ILPSDRSingleWrite data for low-speed interface1.55
LS_CLKC13ILPSDRSingleClock for low-speed interface1.65
DMD_DEN_ARSTZD12ILPSDRSingleAsynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode.1.57
LS_RDATAD13OLPSDRSingle1.43
POWER
VBIAS(3)A13PowerSupply voltage for positive bias level at micromirrors
VOFFSET(3)E13PowerSupply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes. Supply voltage for offset level at micromirrors.
VRESET(3)A14PowerSupply voltage for negative reset level at micromirrors.
VDDB12PowerSupply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs. Supply voltage for normal high level at micromirror address electrodes.
VDDB14Power
VDDC1Power
VDDC14Power
VDDC2Power
VDDE14Power
VDDIB1PowerSupply voltage for SubLVDS receivers.
VDDID1Power
VSSA1GroundCommon return. Ground for all power.
VSSA12Ground
VSSB13Ground
VSSB2Ground
VSSB3Ground
VSSD14Ground
VSSD2Ground
VSSD3Ground
VSSE1Ground
VSSE12Ground
(1) The low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR). See JESD209B.
(2) Net trace lengths inside the package:
The relative dielectric constant for the FQP ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769in/ns.
Propagation delay = 0.265ns/inch = 265ps/in = 10.43ps/mm.
(3) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.
Table 4-2 Test Pads
NUMBERSYSTEM BOARD
A5Do not connect
A6Do not connect
A7Do not connect
A8Do not connect
A9Do not connect
A10Do not connect
A11Do not connect