JAJSN52D October   2021  – October 2024 DLP160CP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
    8. 5.8  Switching Characteristics
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application—nHD Mode
      2. 7.2.2 Typical Application—HD Mode
      3. 7.2.3 Design Requirements
      4. 7.2.4 Detailed Design Procedure
      5. 7.2.5 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 Power Supply Power-Up Procedure
    2. 8.2 Power Supply Power-Down Procedure
    3. 8.3 Power Supply Sequencing Requirements
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
      2. 10.1.2 Device Nomenclature
      3. 10.1.3 Device Markings
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.4 Recommended Operating Conditions

Over-operating free-air temperature range (unless otherwise noted)(1) (2)
MINNOMMAXUNIT
SUPPLY VOLTAGE RANGE(3)
VDDSupply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface		1.651.81.95V
VDDISupply voltage for SubLVDS receivers1.651.81.95V
VOFFSETSupply voltage for HVCMOS and micromirror electrode(4)9.51010.5V
VBIASSupply voltage for micromirror electrode17.51818.5V
VRESETSupply voltage for micromirror electrode–14.5–14–13.5V
|VDDI–VDD|Supply voltage delta (absolute value)(5)0.3V
|VBIAS–VOFFSET|Supply voltage delta (absolute value)(6)10.5V
|VBIAS–VRESET|Supply voltage delta (absolute value)(7)33V
CLOCK FREQUENCY
ƒclockClock frequency for low speed interface LS_CLK(8)108120MHz
ƒclockClock frequency for high speed interface DCLK(9)300540MHz
Duty cycle distortion DCLK44%56%
SUBLVDS INTERFACE(9)
|VID|SubLVDS input differential voltage (absolute value). See Figure 5-8, Figure 5-9150250350mV
VCMCommon mode voltage. See Figure 5-8, Figure 5-97009001100mV
VSUBLVDSSubLVDS voltage. See Figure 5-8, Figure 5-95751225mV
ZLINELine differential impedance (PWB/trace)90100110Ω
ZINInternal differential termination resistance. See Figure 5-1080100120Ω
100Ω differential PCB trace6.35152.4mm
ENVIRONMENTAL
TARRAYArray Temperature – long-term operational(10) (11) (12) (13)040 to 70(12)°C
Array Temperature – short-term operational, 25 hr max(11) (14)-20–10°C
Array Temperature – short-term operational, 500 hr max(11) (14)-100°C
Array Temperature – short-term operational, 500 hr max(11) (14)7075°C
TWINDOWWindow Temperature – operational(15) (16)90°C
|TDELTA|Absolute temperature delta between any point on the window edge and the ceramic test point TP1(17)15°C
TDP-AVGAverage dew point temperature (non-condensing) (18)24°C
TDP-ELRElevated dew point temperature range (non-condensing) (19)2836°C
CTELRCumulative time in elevated dew point temperature range6months
ILLUMINATION
ILLUVIllumination power at wavelengths < 410nm(10)10mW/cm2
ILLVISIllumination power at wavelengths ≥ 410nm and ≤ 800nm(20)26.1W/cm2
ILLIRIllumination power at wavelengths > 800nm10mW/cm2
ILLBLUIllumination power at wavelengths ≥ 410nm and ≤ 475nm(20)8.3W/cm2
ILLBLU1Illumination power at wavelengths ≥ 410nm and ≤ 445nm(20)1.5W/cm2
ILLθIllumination marginal ray angle(15)55deg
(1) The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Section 5.4. No level of performance is implied when operating the device above or below the Section 5.4 limits.
(2) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(3) All voltage values are with respect to the ground pins (VSS).
(4) VOFFSET supply transients must fall within specified max voltages.
(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(7) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit.
(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
(9) Refer to the SubLVDS timing requirements in Section 5.7.
(10) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will reduce the device's lifetime.
(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 6-1 and the package thermal resistance using Section 6.6.
(12) Per Figure 5-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 6.8 for a definition of micromirror landed duty cycle.
(13) Long-term is defined as the usable life of the device.
(14) Short-term is the total cumulative time over the useful life of the device.
(15) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including at the pond of micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document and may negatively affect lifetime.
(16) Window temperature is the highest temperature on the window edge shown in Figure 6-1. The location of thermal test point TP2 in Figure 6-1 is intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.
(17) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 6-1. The window test point TP2 shown in Figure 6-1 is intended to result in the worst-case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
(18) The average over time (including storage and operating) that the device is not in the 'elevated dew point temperature range'.
(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR.
(20) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (TARRAY).
DLP160CP Maximum Recommended Array Temperature — Derating CurveFigure 5-1 Maximum Recommended Array Temperature — Derating Curve