JAJSGY9 データシート

JAJSGY9C february 2019 – july 2023 DLP2010

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FQJ|40
- MCLG028B

サーマルパッド・メカニカル・データ

発注情報

jajsgy9c_oa

6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

			MIN	NOM	MAX	UNIT
LPSDR
t_R	Rise slew rate⁽¹⁾	(30% to 80%) × VDD, Figure 6-3	1		3	V/ns
t_F	Fall slew rate⁽¹⁾	(70% to 20%) × VDD, Figure 6-3	1		3	V/ns
t_R	Rise slew rate⁽²⁾	(20% to 80%) × VDD, Figure 6-3	0.25			V/ns
t_F	Fall slew rate⁽²⁾	(80% to 20%) × VDD, Figure 6-3	0.25			V/ns
t_C	Cycle time LS_CLK,	Figure 6-2	7.7	8.3		ns
t_W(H)	Pulse duration LS_CLK high	50% to 50% reference points, Figure 6-2	3.1			ns
t_W(L)	Pulse duration LS_CLK low	50% to 50% reference points, Figure 6-2	3.1			ns
t_SU	Setup time	LS_WDATA valid before LS_CLK ↑, Figure 6-2	1.5			ns
t_H	Hold time	LS_WDATA valid after LS_CLK ↑, Figure 6-2	1.5			ns
t_WINDOW	Window time⁽¹⁾⁽³⁾	Setup time + Hold time, Figure 6-2	3.0			ns
t_DERATING	Window time derating⁽¹⁾⁽³⁾	For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 6-5		0.35		ns
SubLVDS
t_R	Rise slew rate	20% to 80% reference points, Figure 6-4	0.7	1		V/ns
t_F	Fall slew rate	80% to 20% reference points, Figure 6-4	0.7	1		V/ns
t_C	Cycle time LS_CLK,	Figure 6-6	1.61	1.67		ns
t_W(H)	Pulse duration DCLK high	50% to 50% reference points, Figure 6-6	0.71			ns
t_W(L)	Pulse duration DCLK low	50% to 50% reference points, Figure 6-6	0.71			ns
t_SU	Setup time	D(0:3) valid before DCLK ↑ or DCLK ↓, Figure 6-6
t_H	Hold time	D(0:3) valid after DCLK ↑ or DCLK ↓, Figure 6-6
t_WINDOW	Window time	Setup time + Hold time, Figure 6-6, Figure 6-7	3.0			ns
t_{LVDS-ENABLE+REFGEN}	Power-up receiver⁽⁴⁾				2000	ns

(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.

(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3.

(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

A. Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR)JESD209B.

Figure 6-2 LPSDR Switching Parameters