JAJSK99B
February 2022 – December 2023
DLP2021-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
概要 (続き)
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Storage Conditions
6.3
ESD Ratings
6.4
Recommended Operating Conditions
12
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Timing Requirements
16
6.8
System Mounting Interface Loads
18
6.9
Micromirror Array Physical Characteristics
20
21
6.10
Micromirror Array Optical Characteristics
6.11
Window Characteristics
6.12
Chipset Component Usage Specification
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Micromirror Array
7.3.2
Double Data Rate (DDR) Interface
7.3.3
Micromirror Switching Control
7.3.4
DMD Voltage Supplies
7.3.5
Logic Reset
7.3.6
Temperature Sensing Diode
7.3.6.1
Temperature Sense Diode Theory
7.4
System Optical Considerations
7.4.1
Numerical Aperture and Stray Light Control
7.4.2
Pupil Match
7.4.3
Illumination Overfill and Alignment
7.5
DMD Image Performance Specification
7.6
Micromirror Array Temperature Calculation
7.7
Micromirror Landed-On/Landed-Off Duty Cycle
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.3
Application Mission Profile Consideration
9
Power Supply Recommendations
9.1
Power Supply Sequencing Requirements
9.1.1
Power Up and Power Down
10
Layout
10.1
Layout Guidelines
10.2
Temperature Diode Pins
11
Device and Documentation Support
11.1
Device Support
11.1.1
Device Nomenclature
11.1.2
Device Markings
11.2
Documentation Support
11.2.1
Related Documentation
11.3
ドキュメントの更新通知を受け取る方法
11.4
サポート・リソース
11.5
Trademarks
11.6
静電気放電に関する注意事項
11.7
Device Handling
11.8
用語集
12
Revision History
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
FQU|64
MCLG044B
サーマルパッド・メカニカル・データ
発注情報
jajsk99b_oa
jajsk99b_pm
Figure 6-2
DMD Mirror and SRAM Control Logic Timing Requirements
Figure 6-3
DMD Data Path and Control Logic Timing Requirements