JAJSK99B February 2022 – December 2023 DLP2021-Q1
PRODUCTION DATA
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
SUPPLY VOLTAGE RANGE | ||||||
VDD | Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface |
1.7 | 1.8 | 1.95 | V | |
VOFFSET | Supply voltage for HVCMOS and micromirror electrode | 8.25 | 8.5 | 8.75 | V | |
VBIAS | Supply voltage for mirror electrode | 15.5 | 16 | 16.5 | V | |
VRESET | Supply voltage for micromirror electrode | –9.5 | –10 | –10.5 | V | |
| VBIAS–VOFFSET | | Supply voltage delta (absolute value) | 8.75 | V | |||
| VBIAS–VFRESET | | Supply voltage delta (absolute value) | 28 | V | |||
LVCMOS Buffers | ||||||
VIH | Positive going threshold voltage | 0.7 | VDD+0.3 | x VDD | ||
VIL | Negative going threshold voltage | –0.3 | 0.3 | x VDD | ||
CLOCK FREQUENCY | ||||||
ƒmax | Clock frequency for high speed interface SAC_CLK | 20 | 76.2 | 80 | MHz | |
DCDIN | Duty Cycle Distortion tolerance SAC_CLK | 30% | 70% | |||
ƒmax | Clock frequency for high speed interface DCLK | 20 | 76.2 | 80 | MHz | |
DCDIN | Duty Cycle Distortion tolerance DCLK | 30% | 70% | |||
TEMPERATURE DIODE | ||||||
ITEMP_DIODE | Max current source into temperature diode | 120 | μA | |||
ENVIRONMENTAL | ||||||
TARRAY | Operating DMD array temperature(3) | –40 | 105 | °C | ||
ILLUV | Illumination, wavelength < 395 nm (2) | 2 | mW/cm 2 | |||
ILLOVERFILL | Illumination overfill maximum heat load in area shown in Illumination Overfill Diagram | 40 | mW/mm 2 |