JAJSF31B November   2017  – June 2019 DLP3030-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DLP DLP3030-Q1のブロック・システム図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Optical Characteristics of the Micromirror Array
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
      7. 7.3.7 Active Array Temperature
      8. 7.3.8 DMD JTAG Interface
    4. 7.4 Optical Performance
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Quality Specification
    6. 7.6 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 HUD Reference Design and LED Controller Reference Design
    3. 8.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
    3. 10.3 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デバイスの項目表記
      2. 11.1.2 デバイスのマーキング
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 デバイスの取り扱い
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

FYJ Package
149-Pin CPGA
Bottom View
DLP3030-Q1 auto_g2_pins.gif

Pin Configurations and Functions

PIN I/O DESCRIPTION TRACE, mm(1)
NAME NO.
DATA(0) F18 LVCMOS input Data bus. Synchronous to rising edge and falling edge of DCLK. 8.059
DATA(1) F20
DATA(2) G20
DATA(3) G19
DATA(4) H19
DATA(5) G18
DATA(6) J20
DATA(7) H20
DATA(8) J19
DATA(9) K18
DATA(10) K19
DATA(11) L20
DATA(12) L18
DATA(13) K20
DATA(14) M18
DCLK N18 Data clock.
LOADB M20 Parallel latch load enable. Synchronous to rising edge and falling edge of DCLK. 10.939
SCTRL N19 Serial control (sync). Synchronous to rising edge and falling edge of DCLK. 6.596
TRC M19 Toggle rate control. Synchronous to rising edge and falling edge of DCLK. 8.617
DAD_BUS A7 Reset control serial bus. Synchronous to rising edge of SAC_CLK. 10.413
RESET_OEZ A5 Active low. Output enable signal for internal reset driver circuitry. 13.37
RESET_STROBE A10 Rising edge on RESET_STROBE latches in the control signals. 13.329
SAC_BUS B9 Stepped address control serial bus. Synchronous to rising edge of SAC_CLK. 12.586
SAC_CLK A8 Stepped address control clock. 12.668
TCK M2 JTAG clock. 10.489
TDI N3 JTAG data input. Synchronous to rising edge of TCK. Bond pad connects to internal pull up resistor. 11.04
TDO M3 LVCMOS output JTAG data output. Synchronous to falling edge of TCK. Tri-state failsafe output buffer. 10.067
TMS R5 LVCMOS input JTAG mode select. Synchronous to rising edge of TCK. Bond pad connects to internal pull up resistor. 10.413
TEMP_MINUS T10 Analog Input Calibrated temperature diode used to assist accurate temperature measurements of DMD die. N/A
TEMP_PLUS T11 N/A
No Connect (Unused) A3, A18, A19, A20, B2, B10, B18, B19, B20, C1, C20, D18, D19, D20, E18, E19, E20, N20, P20, R18, R19, R20, T18, T19, T20 N/A N/A N/A
VBIAS(2) F3, K3, L3 Power Power supply for positive bias level of mirror reset signal. N/A
VCC(2) A9, A12, A14, A16, B13, B16, R12, R13, R16, R17, T13, T14, T16 Power supply for low voltage CMOS logic. Power supply for normal high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal during power down. N/A
VCCH P3, R3, T3, T4, T5, T6 Connect to GND Reserved pin. N/A
VOFFSET(2) D1, E1, M1, N1 Power Power supply for high voltage CMOS logic. Power supply for stepped high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal. N/A
VREF(2) B11, B12 Power supply for low voltage CMOS DDR interface. N/A
VRESET(2) B3, C3, E3 Power supply for negative reset level of mirror reset signal. N/A
VSS(2) A6, A11, A13, A15, A17, B4, B5, B8, B14, B15, B17, C2, C18, C19, F1, F2, F19, H1, H2, H3, H18, J18, K1, K2, L19, N2, P18, P19, R4, R14, R15, T7, T9, T12, T15, T17 Common return for all power. N/A
VSSH P1, P2, R1, R2, T1, T2 Connect to GND Reserved pin. N/A
RESERVED_BIM T8 Connect to GND Bond pad connects to internal pull down resistor. N/A
RESERVED_DT R7 N/A
RESERVED_RM E2 N/A
RESERVED_R(0) G1 Do not connect Bond pad connects to 250k pull down resistor. Manufacturing test. N/A
RESERVED_R(1) G2 N/A
RESERVED_R(2) G3 N/A
RESERVED_R(3) J1 N/A
RESERVED_R(4) J2 N/A
RESERVED_R(5) J3 N/A
RESERVED_R(6) L1 N/A
RESERVED_R(7) L2 N/A
RESERVED_PFE R6 Connect to GND Bond pad connects to internal pull down resistor. N/A
RESERVED_RA(0) B6 N/A
RESERVED_RA(1) D3 N/A
RESERVED_RA(2) B7 N/A
RESERVED_RS(0) A4 N/A
RESERVED_RS(1) D2 N/A
RESERVED_SO R9 Do not connect Tri-state failsafe output buffer. N/A
RESERVED_TP(0) R8 Connect to GND Manufacturing test. N/A
RESERVED_TP(1) R10 N/A
RESERVED_TP(2) R11 N/A
(1) Propagation delay is 10.24 ps/mm for the DMD Series 450 ceramic package trace lengths.
(2) The following power supplies are required to operate the DMD: VBIAS, VCC, VOFFSET, VREF, VRESET, VSS.