JAJSGK1D november   2018  – july 2023 DLP3310

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
MIN NOM MAX UNIT
LPSDR
tr Rise slew rate(1) (30% to 80%) × VDD. See Figure 6-3. 1 3 V/ns
tƒ Fall slew rate(1) (70% to 20%) × VDD. See Figure 6-3. 1 3 V/ns
tr Rise slew rate(2) (20% to 80%) × VDD. See Figure 6-3. 0.25 V/ns
tƒ Fall slew rate(2) (80% to 20%) × VDD. See Figure 6-3. 0.25 V/ns
tc Cycle time LS_CLK, See Figure 6-2. 7.7 8.3 ns
tW(H) Pulse duration LS_CLK high 50% to 50% reference points. See Figure 6-2. 3.1 ns
tW(L) Pulse duration LS_CLK low 50% to 50% reference points. See Figure 6-2. 3.1 ns
tsu Setup time LS_WDATA valid before LS_CLK ↑. See Figure 6-2. 1.5 ns
th Hold time LS_WDATA valid after LS_CLK ↑. See Figure 6-2. 1.5 ns
tWINDOW Window time(1) (3) Setup time + Hold time, Figure 6-2 3 ns
tDERATING Window time derating(1) (3) For each 0.25 V/ns reduction in slew rate below 1 V/ns. See Figure 6-5. 0.35 ns
SubLVDS
tr Rise slew rate 20% to 80% reference points. See Figure 6-4. 0.7 1 V/ns
tƒ Fall slew rate 80% to 20% reference points. See Figure 6-4. 0.7 1 V/ns
tc Cycle time DCLK See Figure 6-6. 1.79 1.85 ns
tW(H) Pulse duration DCLK high 50% to 50% reference points. See Figure 6-6. 0.79 ns
tW(L) Pulse duration DCLK low 50% to 50% reference points. See Figure 6-6. 0.79 ns
tsu Setup time D(0:7) valid before
DCLK ↑ or DCLK ↓. See Figure 6-6.
th Hold time D(0:7) valid after
DCLK ↑ or DCLK ↓. See Figure 6-6.
tWINDOW Window time Setup time + Hold time. See Figure 6-6, Figure 6-7. 3.0 ns
tLVDS-ENABLE+REFGEN Power-up receiver(4) 2000 ns
(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.
(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3.
(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
GUID-BB969F5E-FED3-42CE-8C24-AC40AC255D38-low.gif
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR)JESD209B.
Figure 6-2 LPSDR Switching Parameters
GUID-353AF840-F97B-4459-ACFF-AFD7F786982F-low.gifFigure 6-3 LPSDR Input Rise and Fall Slew Rate
GUID-4E20CDD2-0C56-4FF6-A768-A35823A14E32-low.gifFigure 6-4 SubLVDS Input Rise and Fall Slew Rate
GUID-6FD74061-9E7B-424F-99BC-3F8C818A1F22-low.gifFigure 6-5 Window Time Derating Concept
GUID-B8436839-256D-4241-B7E8-96E93F952F08-low.gifFigure 6-6 SubLVDS Switching Parameters
GUID-33B064E4-291F-4949-AC2B-DFAA49B52495-low.gif
Note: Refer to High Speed Interface for details.
Figure 6-7 High-Speed Training Scan Window
GUID-C59A9906-EA5A-482C-91E6-6AD1EA449012-low.gifFigure 6-8 SubLVDS Voltage Parameters
GUID-B21DB16E-0F7A-4E25-9247-79DB7F0D0B95-low.gifFigure 6-9 SubLVDS Waveform Parameters
GUID-53D0329D-CD7E-419E-BDC3-04B9E308E69C-low.gifFigure 6-10 SubLVDS Equivalent Input Circuit
GUID-56923680-876C-4099-B60C-AF51DC860B61-low.gifFigure 6-11 LPSDR Input Hysteresis
GUID-7B52EAD3-43B1-4AC9-8685-10B0E16540B5-low.gifFigure 6-12 LPSDR Read Out
GUID-EF432CDC-064E-4862-9823-9BA35705CA63-low.gif
See Timing for more information.
Figure 6-13 Test Load Circuit for Output Propagation Measurement