JAJSPI5B December   2022  – August 2024 DLP4621-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
      1. 5.4.1 Illumination Overfill Diagram
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
      1.      Electrical and Timing Diagrams
    8. 5.8  Switching Characteristics
      1. 5.8.1 LPSDR and Test Load Circuit Diagrams
    9. 5.9  System Mounting Interface Loads
      1.      System Interface Loads Diagram
    10. 5.10 Micromirror Array Physical Characteristics
      1. 5.10.1 Micromirror Array Physical Characteristics Diagram
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 SubLVDS Data Interface
      2. 6.3.2 Low Speed Interface for Control
      3. 6.3.3 DMD Voltage Supplies
      4. 6.3.4 Asynchronous Reset
      5. 6.3.5 Temperature Sensing Diode
        1. 6.3.5.1 Temperature Sense Diode Theory
    4. 6.4 System Optical Considerations
      1. 6.4.1 Numerical Aperture and Stray Light Control
      2. 6.4.2 Pupil Match
      3. 6.4.3 Illumination Overfill
    5. 6.5 DMD Image Performance Specification
    6. 6.6 Micromirror Array Temperature Calculation
      1. 6.6.1 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 6.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Overview
      2. 7.2.2 Input Image Resolution
      3. 7.2.3 Reference Design
      4. 7.2.4 Application Mission Profile Consideration
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply Power-Up Procedure
      2. 7.3.2 Power Supply Power-Down Procedure
      3. 7.3.3 Power Supply Sequencing Requirements
    4. 7.4 Layout Guidelines
    5. 7.5 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 サード・パーティ製品に関する免責事項
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 DMD Handling
    8. 8.8 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • FQX|120
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

DLP4621-Q1 FQX Package 120-Pin LGA Bottom View Figure 4-1 FQX Package 120-Pin LGA Bottom View
Table 4-1 Pin Functions—Connector Pins
PIN TYPE SIGNAL DATA RATE DESCRIPTION
NAME NO.
DATA INPUTS
D_AN(0)

A3

 I SubLVDS Double Data, Negative
D_AN(1)

B1

 I SubLVDS Double Data, Negative
D_AN(2)

C2

 I SubLVDS Double Data, Negative
D_AN(3)

F2

 I SubLVDS Double Data, Negative
D_AN(4)

H2

 I SubLVDS Double Data, Negative
D_AN(5)

K1

 I SubLVDS Double Data, Negative
D_AN(6)

K4

 I SubLVDS Double Data, Negative
D_AN(7)

K6

 I SubLVDS Double Data, Negative
D_AP(0) A2 I SubLVDS Double Data, Positive
D_AP(1)

C1

 I SubLVDS Double Data, Positive
D_AP(2)

D2

 I SubLVDS Double Data, Positive
D_AP(3)

E2

 I SubLVDS Double Data, Positive
D_AP(4)

G2

 I SubLVDS Double Data, Positive
D_AP(5)

K2

 I SubLVDS Double Data, Positive
D_AP(6)

K3

 I SubLVDS Double Data, Positive
D_AP(7)

K5

 I SubLVDS Double Data, Positive
D_BN(0)

A22

 I SubLVDS Double Data, Negative
D_BN(1)

B24

 I SubLVDS Double Data, Negative
D_BN(2)

D23

 I SubLVDS Double Data, Negative
D_BN(3)

F23

 I SubLVDS Double Data, Negative
D_BN(4)

H23

 I SubLVDS Double Data, Negative
D_BN(5)

K24

 I SubLVDS Double Data, Negative
D_BN(6)

K21

 I SubLVDS Double Data, Negative
D_BN(7)

K19

 I SubLVDS Double Data, Negative
D_BP(0)

A23

 I SubLVDS Double Data, Positive
D_BP(1)

C24

 I SubLVDS Double Data, Positive
D_BP(2)

C23

 I SubLVDS Double Data, Positive
D_BP(3)

E23

 I SubLVDS Double Data, Positive
D_BP(4)

G23

 I SubLVDS Double Data, Positive
D_BP(5)

K23

 I SubLVDS Double Data, Positive
D_BP(6)

K22

 I SubLVDS Double Data, Positive
D_BP(7)

K20

 I SubLVDS Double Data, Positive
DCLK_AN

J1

 I SubLVDS Double Clock, Negative
DCLK_AP

H1

 I SubLVDS Double Clock, Positive
DCLK_BN

J24

 I SubLVDS Double Clock, Negative
DCLK_BP

H24

 I SubLVDS Double Clock, Positive
LS_CLKN

C3

 I SubLVDS Single Clock for Low Speed Interface, Negative
LS_CLKP

C4

 I SubLVDS Single Clock for Low Speed Interface, Positive
LS_WDATAN

C5

 I SubLVDS Single Write Data for Low Speed Interface, Negative
LS_WDATAP

C6

 I SubLVDS Single Write Data for Low Speed Interface, Positive
CONTROL INPUTS
DMD_DEN_ARSTZ

E6

 I LPSDR Asynchronous Reset Active Low. Logic High Enables DMD
LS_RDATA_A

E19

 O LPSDR Single Read Data for Low Speed Interface
LS_RDATA_B

F19

 O LPSDR Single Read Data for Low Speed Interface
TEMPERATURE SENSE DIODE
TEMP_N

F6

 O Calibrated temperature diode used to assist accurate temperature measurements of DMD die
TEMP_P

G6

 I
POWER
VBIAS A4 Power Supply voltage for positive bias level at micromirrors
VBIAS

A21

 Power
VOFFSET

B3

 Power Supply voltage for high-voltage CMOS core logic. Supply voltage for offset level at micromirrors
VOFFSET

B4

 Power
VOFFSET

B21

 Power
VOFFSET

B22

 Power
VOFFSET

J4

 Power
VOFFSET

J21

 Power
VRESET

B6

 Power Supply voltage for negative reset level at micromirrors
VRESET

B19

 Power
VDD A5 Power Supply voltage for Low Voltage CMOS core logic; for LPSDR inputs; for normal high level at micromirror address electrodes
VDD A20 Power
VDD

C20

 Power
VDD

D4

 Power
VDD

D19

 Power
VDD

D21

 Power
VDD

E3

 Power
VDD

E22

 Power
VDD

F4

 Power
VDD

G3

 Power
VDD

G21

 Power
VDD

H22

 Power
VDD

J3

 Power
VDD

J6

 Power
VDD

J19

 Power
VDDI

E5

 Power Supply voltage for SubLVDS receivers
VDDI

E20

 Power
VDDI

F5

 Power
VDDI

F20

 Power
VDDI

G5

 Power
VDDI

G20

 Power
VDDI

H5

 Power
VDDI

H20

 Power
VSS

A1

 Ground Common return. Ground for all power
VSS A6 Ground
VSS A19 Ground
VSS

A24

 Ground
VSS B2 Ground
VSS

B5

 Ground
VSS B20 Ground
VSS B23 Ground
VSS C19 Ground
VSS C21 Ground
VSS C22 Ground
VSS D3 Ground
VSS

D5

 Ground
VSS

D6

 Ground
VSS

D20

 Ground
VSS

D22

 Ground
VSS

E4

 Ground
VSS

E21

 Ground
VSS

F3

 Ground
VSS

F21

 Ground
VSS

F22

 Ground
VSS

G4

 Ground
VSS

G19

 Ground
VSS

G22

 Ground
VSS

H3

 Ground
VSS

H4

 Ground
VSS

H6

 Ground
VSS

H19

 Ground
VSS

H21

 Ground
VSS

J2

 Ground
VSS

J5

 Ground
VSS

J20

 Ground
VSS

J22

 Ground
VSS

J23

 Ground
Table 4-2 Pin Functions—Test Pads
Pin Number SYSTEM BOARD
C17 Do not connect.
C18 Do not connect.
D16 Do not connect. Internally connected to VSS

D17

 Do not connect.
D18 Do not connect.
E16 Do not connect.
E17 Do not connect.
E18 Do not connect.