JAJSI71 データシート

JAJSI71C April 2019 – February 2023 DLP470NE

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FXH|257
- MCSS006B

サーマルパッド・メカニカル・データ

発注情報

jajsi71c_oa

6.1 Absolute Maximum Ratings

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

		MIN	MAX	UNIT
SUPPLY VOLTAGES
V_CC	Supply voltage for LVCMOS core logic⁽¹⁾	–0.5	2.3	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode⁽¹⁾⁽²⁾	–0.5	11	V
V_BIAS	Supply voltage for micromirror electrode⁽¹⁾	–0.5	19	V
V_RESET	Supply voltage for micromirror electrode⁽¹⁾	–15	–0.3	V
\|V_BIAS – V_OFFSET\|	Supply voltage difference (absolute value)⁽³⁾		11	V
\|V_BIAS – V_RESET\|	Supply voltage difference (absolute value)⁽⁴⁾		34	V
INPUT VOLTAGES
	Input voltage for all other LVCMOS input pins⁽¹⁾	–0.5	V_CC + 0.5	V
\|V_ID\|	Input differential voltage (absolute value)⁽⁵⁾		500	mV
I_ID	Input differential current⁽⁶⁾		6.3	mA
Clocks
ƒ_CLOCK	Clock frequency for LVDS interface, DCLK_C		400	MHz
ƒ_CLOCK	Clock frequency for LVDS interface, DCLK_D		400	MHz
ENVIRONMENTAL
T_ARRAY and T_WINDOW	Temperature, operating⁽⁷⁾	0	90	°C
T_ARRAY and T_WINDOW	Temperature, non–operating⁽⁷⁾	–40	90	°C
\|T_DELTA\|	Absolute temperature delta between any point on the window edge and the ceramic test point TP1 ⁽⁸⁾		30	°C
T_DP	Dew point temperature, operating and non–operating (noncondensing)		81	°C

(1) All voltages are referenced to common ground V_SS. V_BIAS, V_CC, V_OFFSET, and V_RESET power supplies are all required for proper DMD operation. V_SS must also be connected.

(2) V_OFFSET supply transients must fall within specified voltages.

(3) Exceeding the recommended allowable voltage difference between V_BIAS and V_OFFSET may result in excessive current draw.

(4) Exceeding the recommended allowable voltage difference between V_BIAS and V_RESET may result in excessive current draw.

(5) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(6) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(7) The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the window edge as defined in Figure 7-2. The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 7-2 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, use that point.

(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-2. The window test points TP2, TP3, TP4 and TP5 shown in Figure 7-2 are intended to result in the worst case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, use that point.